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Commit 4cdaba1b authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Andi Shyti
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drm/i915: Reoder BDW+ EU/slice fuse bits


We customarily define the bits of a register in big endian
order. Reorder the BDW+ fuse bits to match.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-11-ville.syrjala@linux.intel.com
parent d7513116
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