<7> [567.413923] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 19, 126, 143, 143, 196, 231, 231, 267, 31, 91, 96 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [567.415193] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] [CRTC:98:pipe A] data rate 0 num active planes 0
<7> [567.416970] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 0: max bw 12447 required 0
<7> [567.418093] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 1: max bw 12447 required 0
<7> [567.419029] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 2: max bw 16761 required 0
<7> [567.419992] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 3: max bw 14636 required 0
<7> [567.421109] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] Modeset required for cdclk change
<7> [567.422033] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 172800 kHz, actual 172800 kHz
<7> [567.423061] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 0, actual 0
<7> [567.424009] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [CRTC:98:pipe A] enable: no [modeset]
<7> [567.425010] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:31:plane 1A] fb: [NOFB], visible: no
<7> [567.425900] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:40:plane 2A] fb: [NOFB], visible: no
<7> [567.426806] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:49:plane 3A] fb: [NOFB], visible: no
<7> [567.427717] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:58:plane 4A] fb: [NOFB], visible: no
<7> [567.429364] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:67:plane 5A] fb: [NOFB], visible: no
<7> [567.430823] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:76:plane 6A] fb: [NOFB], visible: no
<7> [567.431705] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:85:plane 7A] fb: [NOFB], visible: no
<7> [567.432600] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:94:cursor A] fb: [NOFB], visible: no
<7> [567.436297] i915 0000:00:02.0: [drm:intel_psr_disable_locked [i915]] Disabling PSR1
<7> [567.440687] i915 0000:00:02.0: [drm:intel_edp_backlight_off [i915]]
<7> [567.646624] i915 0000:00:02.0: [drm:intel_backlight_set_pwm_level [i915]] set backlight PWM = 0
<7> [567.649815] i915 0000:00:02.0: [drm:intel_disable_transcoder [i915]] disabling pipe A
<7> [567.661983] i915 0000:00:02.0: [drm:intel_pps_off_unlocked [i915]] Turn [ENCODER:307:DDI A/PHY A] panel power off
<7> [567.663330] i915 0000:00:02.0: [drm:intel_pps_off_unlocked [i915]] Wait for panel power off time
<7> [567.665428] i915 0000:00:02.0: [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
<7> [567.716611] i915 0000:00:02.0: [drm:wait_panel_status [i915]] Wait complete
<7> [567.717891] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DDI_IO_A
<7> [567.719731] i915 0000:00:02.0: [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x00010000, dig 0x0000008a, pins 0x00000010, long 0x00000010
<7> [567.720526] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling AUX_A
<7> [567.720799] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] digital hpd on [ENCODER:307:DDI A/PHY A] - long
<7> [567.722088] i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 0x1, on? 1) for [CRTC:98:pipe A]
<7> [567.722165] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 10
<7> [567.723733] i915 0000:00:02.0: [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP [ENCODER:307:DDI A/PHY A]
<7> [567.723909] i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
<7> [567.725450] i915 0000:00:02.0: [drm:intel_cdclk_dump_config [i915]] Changing CDCLK to 172800 kHz, VCO 345600 kHz, ref 38400 kHz, bypass 19200 kHz, voltage level 0
<7> [567.727841] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:307:DDI A/PHY A]
<7> [567.730005] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:316:DDI B/PHY B]
<7> [567.731333] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:325:DDI TC1/PHY TC1]
<7> [567.732190] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:327:DP-MST A]
<7> [567.733137] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:328:DP-MST B]
<7> [567.734131] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:329:DP-MST C]
<7> [567.735066] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:330:DP-MST D]
<7> [567.735967] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:335:DDI TC2/PHY TC2]
<7> [567.736890] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:337:DP-MST A]
<7> [567.738159] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:338:DP-MST B]
<7> [567.739071] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:339:DP-MST C]
<7> [567.739925] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:340:DP-MST D]
<7> [567.740771] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:344:DDI TC3/PHY TC3]
<7> [567.741708] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:346:DP-MST A]
<7> [567.742592] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:347:DP-MST B]
<7> [567.743468] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:348:DP-MST C]
<7> [567.744328] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:349:DP-MST D]
<7> [567.745108] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:353:DDI TC4/PHY TC4]
<7> [567.745968] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:355:DP-MST A]
<7> [567.746938] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:356:DP-MST B]
<7> [567.747860] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:357:DP-MST C]
<7> [567.748707] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:358:DP-MST D]
<7> [567.749544] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:308:eDP-1]
<7> [567.750593] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 0
<7> [567.751578] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 1
<7> [567.752606] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TBT PLL
<7> [567.753570] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TC PLL 1
<7> [567.754490] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TC PLL 2
<7> [567.755426] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TC PLL 3
<7> [567.756403] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TC PLL 4
<7> [567.757348] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TC PLL 5
<7> [567.758306] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] TC PLL 6
<7> [567.759526] i915 0000:00:02.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x3
<7> [567.760574] i915 0000:00:02.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x1
<7> [567.761901] i915 0000:00:02.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:98:pipe A]
<7> [567.832908] intel_gt_set_wedged called from intel_gt_set_wedged_on_fini+0x9/0x30 [i915]
<7> [568.142526] i915 0000:00:02.0: [drm:drm_client_release] drm_fb_helper
<7> [568.148736] i915 0000:00:02.0: [drm:i915_hdcp_component_unbind [i915]] I915 HDCP comp unbind
<7> [568.687548] i915 0000:00:02.0: [drm:i915_driver_probe [i915]] WOPCM: 2048K
<7> [568.689358] i915 0000:00:02.0: [drm:intel_uc_init_early [i915]] enable_guc=2 (guc:yes submission:no huc:yes slpc:no)
<7> [568.691074] i915 0000:00:02.0: [drm:intel_pch_type [i915]] Found Tiger Lake LP PCH