[CML] All tests - *ERROR* CPU pipe [ABCD] FIFO underrun

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html#dmesg-warnings128

<7> [153.810934] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:132] 1920x1080 format = XR24 little-endian (0x34325258) modifier = 0x100000000000001, visible: yes
<7> [153.811015] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] 	rotation: 0x1, scaler: -1
<7> [153.811095] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] 	src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0
<7> [153.811226] i915 0000:00:02.0: [drm:intel_psr_disable_locked [i915]] Disabling PSR2
<3> [153.843335] i915 0000:00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun
<7> [153.843437] i915 0000:00:02.0: [drm:intel_fbc_underrun_work_fn [i915]] Disabling FBC due to FIFO underrun.
<7> [153.857795] i915 0000:00:02.0: [drm:intel_psr_post_plane_update [i915]] Enabling PSR1
<7> [153.858471] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
<7> [153.858574] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:51:pipe A]
<7> [153.858753] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.94 [i915]] DPLL 0