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GEN9 ICL TGL: igt@i915_pm_dc@dc5-dpms - fail - Failed assertion: dc_state_wait_entry(data->debugfs_fd, dc_flag, prev_dc_count), DC5 state is not achieved

https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5872/shard-tglb8/igt@i915_pm_dc@dc5-dpms.html

Starting subtest: dc5-dpms
(i915_pm_dc:1865) CRITICAL: Test assertion failure function check_dc_counter, file ../tests/i915/i915_pm_dc.c:217:
(i915_pm_dc:1865) CRITICAL: Failed assertion: dc_state_wait_entry(data->debugfs_fd, dc_flag, prev_dc_count)
(i915_pm_dc:1865) CRITICAL: DC5 state is not achieved
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