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TGL: igt@i915_pm_rc6_residency@rc6-idle - fail - Failed assertion: 2 * phases[2].power - phases[0].power <= phases[1].power, Exceeded energy expectations for single busy wait load

http://gfx-ci.fi.intel.com/cibuglog-ng/testresult/788200311?query_key=3d424b60b321280c1b2e06b3b234fd1bf57bdc2a

Starting subtest: rc6-idle
(i915_pm_rc6_residency:1112) WARNING: Total energy used while idle: 34.5mJ
(i915_pm_rc6_residency:1112) CRITICAL: Test assertion failure function rc6_idle, file ../tests/i915/i915_pm_rc6_residency.c:447:
(i915_pm_rc6_residency:1112) CRITICAL: Failed assertion: 2 * phases[2].power - phases[0].power <= phases[1].power
(i915_pm_rc6_residency:1112) CRITICAL: Exceeded energy expectations for single busy wait load
Used 58.8mW, min 46.9mW, max 65.2mW, expected less than 56.0mW
Subtest rc6-idle failed.
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