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HSW SNB IVB igt@prime_vgem@coherency-blt - fail - Failed assertion: foreign[scratch.pitch * i / sizeof(*foreign)] == i ; error: 0 != 0xcb

  • Starting subtest: coherency-blt
  • (prime_vgem:1303) CRITICAL: Test assertion failure function test_blt_interleaved, file ../tests/prime_vgem.c:533:
  • (prime_vgem:1303) CRITICAL: Failed assertion: foreign[scratch.pitch * i / sizeof(*foreign)] == i
  • (prime_vgem:1303) CRITICAL: error: 0 != 0xcb
  • Subtest coherency-blt failed.
  • **** DEBUG ****
  • (prime_vgem:1303) CRITICAL: Test assertion failure function test_blt_interleaved, file ../tests/prime_vgem.c:533:
  • (prime_vgem:1303) CRITICAL: Failed assertion: foreign[scratch.pitch * i / sizeof(*foreign)] == i
  • (prime_vgem:1303) CRITICAL: error: 0 != 0xcb
  • (prime_vgem:1303) igt_core-INFO: Stack trace:
  • (prime_vgem:1303) igt_core-INFO: #0 ../lib/igt_core.c:1727 __igt_fail_assert()
  • (prime_vgem:1303) igt_core-INFO: #1 (moved) ../tests/prime_vgem.c:542 __real_main1064()
  • (prime_vgem:1303) igt_core-INFO: #2 [+0x0]
  • **** END ****
  • Subtest coherency-blt: FAIL (6.570s)
  • Dmesg
  • <6> [146.118648] Console: switching to colour dummy device 80x25
  • <6> [146.118796] [IGT] prime_vgem: executing
  • <6> [146.166119] [IGT] prime_vgem: starting subtest coherency-blt
  • <3> [146.194313] DMAR: DRHD: handling fault status reg 2
  • <3> [146.194368] DMAR: [DMA Write] Request device [00:02.0] PASID ffffffff fault addr fffff000 [fault reason 05] PTE Write access is not set
  • <3> [146.195968] DMAR: DRHD: handling fault status reg 2
  • <3> [146.196021] DMAR: [DMA Write] Request device [00:02.0] PASID ffffffff fault addr fffff000 [fault reason 05] PTE Write access is not set
  • <3> [146.196482] DMAR: DRHD: handling fault status reg 2
  • <3> [146.196568] DMAR: [DMA Write] Request device [00:02.0] PASID ffffffff fault addr fffff000 [fault reason 05] PTE Write access is not set
  • <3> [146.197234] DMAR: DRHD: handling fault status reg 2
  • <7> [152.465446] heartbeat bcs0 heartbeat {seqno:13:448, prio:-2147483648} not ticking
  • <7> [152.465451] heartbeat Awake? 4
  • <7> [152.465454] heartbeat Barriers?: no
  • <7> [152.465456] heartbeat Latency: 193us
  • <7> [152.465459] heartbeat Forcewake: 0 domains, 0 active
  • <7> [152.465462] heartbeat Heartbeat: 3008 ms ago
  • <7> [152.465466] heartbeat Reset count: 0 (global 1)
  • <7> [152.465469] heartbeat Properties:
  • <7> [152.465472] heartbeat heartbeat_interval_ms: 2500 [default 2500]
  • <7> [152.465475] heartbeat max_busywait_duration_ns: 8000 [default 8000]
  • <7> [152.465477] heartbeat preempt_timeout_ms: 640 [default 640]
  • <7> [152.465480] heartbeat stop_timeout_ms: 100 [default 100]
  • <7> [152.465483] heartbeat timeslice_duration_ms: 1 [default 1]
  • <7> [152.465485] heartbeat Requests:
  • <7> [152.465499] heartbeat active 13:1bf*- @ 6045ms: prime_vgem[1303]
  • <7> [152.465502] heartbeat ring->start: 0x7fc8b000
  • <7> [152.465505] heartbeat ring->head: 0x00003458
  • <7> [152.465507] heartbeat ring->tail: 0x00003a20
  • <7> [152.465510] heartbeat ring->emit: 0x00003a20
  • <7> [152.465512] heartbeat ring->space: 0x000035c8
  • <7> [152.465514] heartbeat ring->hwsp: 0x7fc8f100
  • <7> [152.465517] heartbeat [head 35f8, postfix 3670, tail 3810, batch 0x00000000_01029000]:
  • <7> [152.465529] heartbeat [0000] 13244001 00000204 00000000 00000000 13204001 00000204 00000000 00000000
  • <7> [152.465532] heartbeat [0020] 11000001 00022220 ffffffff 11000001 00022228 7fc90000 12400001 00022228
  • <7> [152.465536] heartbeat [0040] 7ffff000 11000001 000220c0 02000200 13204001 00000204 00000000 00000000
  • <7> [152.465539] heartbeat [0060] 13244001 00000204 00000000 00000000 18800100 01029000 13244001 00000104
  • <7> [152.465542] heartbeat [0080] 000001bf 10800001 00000100 000001bf 10800001 00000100 000001bf 10800001
  • <7> [152.465546] heartbeat [00a0] 00000100 000001bf 10800001 00000100 000001bf 10800001 00000100 000001bf
  • <7> [152.465549] heartbeat [00c0] 10800001 00000100 000001bf 10800001 00000100 000001bf 10800001 00000100
  • <7> [152.465552] heartbeat [00e0] 000001bf 10800001 00000100 000001bf 10800001 00000100 000001bf 10800001
  • <7> [152.465556] heartbeat [0100] 00000100 000001bf 10800001 00000100 000001bf 10800001 00000100 000001bf
  • <7> [152.465559] heartbeat [0120] 10800001 00000100 000001bf 10800001 00000100 000001bf 10800001 00000100
  • <7> [152.465562] heartbeat [0140] 000001bf 10800001 00000100 000001bf 10800001 00000100 000001bf 10800001
  • <7> [152.465565] heartbeat [0160] 00000100 000001bf 10800001 00000100 000001bf 10800001 00000100 000001bf
  • <7> [152.465569] heartbeat [0180] 10800001 00000100 000001bf 10800001 00000100 000001bf 10800001 00000100
  • <7> [152.465572] heartbeat [01a0] 000001bf 10800001 00000100 000001bf 10800001 00000100 000001bf 10800001
  • <7> [152.465575] heartbeat [01c0] 00000100 000001bf 10800001 00000100 000001bf 10800001 00000100 000001bf
  • <7> [152.465578] heartbeat [01e0] 10800001 00000100 000001bf 10800001 00000100 000001bf 10800001 00000100
  • <7> [152.465582] heartbeat [0200] 000001bf 13000001 00000000 00000000 01000000 00000000
  • <7> [152.465588] heartbeat On hold?: 0
  • <7> [152.465591] heartbeat MMIO base: 0x00022000
  • <7> [152.465600] heartbeat RING_START: 0x7fc8b000
  • <7> [152.465605] heartbeat RING_HEAD: 0x00003670
  • <7> [152.465609] heartbeat RING_TAIL: 0x00003a20
  • <7> [152.465614] heartbeat RING_CTL: 0x00003001
  • <7> [152.465620] heartbeat RING_MODE: 0x00000000
  • <7> [152.465624] heartbeat RING_IMR: 0xffbfffff
  • <7> [152.465628] heartbeat RING_ESR: 0x00000001
  • <7> [152.465632] heartbeat RING_EMR: 0xffffffff
  • <7> [152.465636] heartbeat RING_EIR: 0x00000000
  • <7> [152.465640] heartbeat ACTHD: 0x00000000_01029004
  • <7> [152.465645] heartbeat BBADDR: 0x00000000_01029001
  • <7> [152.465649] heartbeat DMA_FADDR: 0x00000000_01029200
  • <7> [152.465653] heartbeat IPEIR: 0x00000008
  • <7> [152.465657] heartbeat IPEHR: 0x7fc90001
  • <7> [152.465661] heartbeat PP_DIR_BASE: 0x7fc90000
  • <7> [152.465665] heartbeat PP_DIR_BASE_READ: 0x00000000
  • <7> [152.465669] heartbeat PP_DIR_DCLV: 0xffffffff
  • <7> [152.465674] heartbeat E 13:1bf*- @ 6045ms: prime_vgem[1303]
  • <7> [152.465678] heartbeat E 13:1c0 @ 3008ms: [i915]
  • <7> [152.465681] heartbeat Switch priority hint: 0
  • <7> [152.465683] heartbeat HWSP:
  • <7> [152.465687] heartbeat [0000] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
  • <7> [152.465689] heartbeat *
  • <7> [152.465693] heartbeat [0100] 000001be 00000000 00000000 00000000 00000000 00000000 00000000 00000000
  • <7> [152.465696] heartbeat [0120] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
  • <7> [152.465699] heartbeat *
  • <7> [152.465707] heartbeat Idle? no
  • <7> [152.465709] heartbeat IRQ: enabled
  • <7> [152.465712] heartbeat Signals:
  • <7> [152.465716] heartbeat [13:1bf*] @ 6045ms
  • <6> [152.466575] i915 0000:00:02.0: [drm] GPU HANG: ecode 7:2:8036fff6, in prime_vgem [1303]
  • <7> [152.467057] i915 0000:00:02.0: [drm:intel_gt_reset_global [i915]] resetting chip, engines=2
  • <5> [152.467238] i915 0000:00:02.0: [drm] Resetting chip for stopped heartbeat on bcs0
  • <5> [152.568816] i915 0000:00:02.0: [drm] prime_vgem[1303] context reset due to GPU hang
  • <7> [152.568963] i915 0000:00:02.0: [drm:__i915_request_reset.cold.61 [i915]] client prime_vgem[1303]: gained 1 ban score, now 1
  • <4> [152.569658] dmar_fault: 1208 callbacks suppressed
  • <3> [152.569661] DMAR: DRHD: handling fault status reg 2
  • <3> [152.569716] DMAR: [DMA Write] Request device [00:02.0] PASID ffffffff fault addr fffff000 [fault reason 05] PTE Write access is not set
  • <6> [152.736935] [IGT] prime_vgem: exiting, ret=98
  • <6> [152.774237] Console: switching to colour frame buffer device 128x48
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