[TGL only] All tests - Encoder config failure: -22

Update: The issue is seen on CI tests also: CI_DRM_8068_resume on re-tgl-u2

http://gfx-ci.fi.intel.com/cibuglog-ng/testresult/584905973?query_key=bb190df7eb94c4af294baf86cc481cdeda1b9492

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/re-tgl-u2/igt@kms_plane_lowres@pipe-b-tiling-none.html

Test results provided by B.S.Karthik n manual testing with 4 Displays on TGL-U. All 4 displays are coming up (visually verified) display_info logs attached : display_info_TGL_A6_4_feb.txt

The IGT : igt@kms_atomic_transition@4x-modeset-transitions-nonblocking fails.

(kms_atomic_transition:866) igt_kms-CRITICAL: Failed assertion: ret == 0
(kms_atomic_transition:866) igt_kms-CRITICAL: Last errno: 22, Invalid argument
(kms_atomic_transition:866) igt_kms-CRITICAL: error: -22 != 0

Dmesg :

7,19963,290196770,-;i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:283:DP-1] Limiting display bpp to 30 instead of EDID bpp 30, requested bpp 36, max platform bpp 36
 SUBSYSTEM=pci
 DEVICE=+pci:0000:00:02.0
7,19964,290196803,-;[drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 270000 max bpp 30 pixel clock 533250KHz
7,19965,290196836,-;[drm:intel_dp_compute_config [i915]] Force DSC en = 0
7,19966,290196867,-;i915 0000:00:02.0: [drm:intel_atomic_check [i915]] Encoder config failure: -22