igt@kms_plane.* - dmesg-warn - *ERROR* CPU pipe A FIFO underrun : transcoder

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11467/shard-dg1-19/igt@kms_plane@pixel-format@pipe-a-planes.html

<7> [688.198277] i915 0000:03:00.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe A
<7> [688.214846] i915 0000:03:00.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe A
<3> [688.248168] i915 0000:03:00.0: [drm] *ERROR* CPU pipe A FIFO underrun: transcoder,
<7> [688.248268] i915 0000:03:00.0: [drm:intel_fbc_underrun_work_fn [i915]] Disabling FBC due to FIFO underrun.
<7> [688.264783] i915 0000:03:00.0: [drm:__intel_fbc_disable [i915]] Disabling FBC on [PLANE:31:plane 1A]
<7> [688.281560] [drm:drm_mode_addfb2] [FB:359]
<7> [688.281650] i915 0000:03:00.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A]   level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7,*twm, swm, stwm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7,*twm, swm, stwm
<7> [688.281708] i915 0000:03:00.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A]   lines    1,   5,   5,   5,   8,   8,   9,  10,   0,   0,    0 ->    3,   5,   5,   5,   8,   8,   9,  10,   0,   0,    0
<7> [688.281761] i915 0000:03:00.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A]  blocks    6,  81,  81,  81, 129, 129, 145, 161,  20,   0,    0 ->    6,  11,  11,  11,  17,  17,  19,  21,  20,   0,    0
<7> [688.281812] i915 0000:03:00.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb    8,  91,  91,  91, 143, 143, 161, 179,  21,   0,    0 ->    8,  14,  14,  14,  20,  20,  22,  25,  21,   0,    0
<7> [688.281995] [drm:drm_mode_addfb2] [FB:359]
<7> [688.282243] [drm:eb_lookup_vmas [i915]] EINVAL at eb_validate_vma:516
<7> [688.282535] i915 0000:03:00.0: [drm:i915_gem_context_create_ioctl [i915]] HW context 1 created