[EHL] igt@kms_cursor_legacy@cursor-vs-flip-varying-size - dmesg-warn - *ERROR* CPU pipe A FIFO underrun: transcoder.

https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_935/fi-ehl-2/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html

<3> [63.650212] i915 0000:00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun: transcoder,
<7> [63.650334] i915 0000:00:02.0: [drm:intel_fbc_underrun_work_fn [i915]] Disabling FBC due to FIFO underrun.
<3> [63.660161] DMAR: DRHD: handling fault status reg 3
<7> [66.588840] i915 0000:00:02.0: [drm:intel_pps_vdd_off_sync_unlocked [i915]] Turning [ENCODER:238:DDI A/PHY A] VDD off
<7> [66.589215] i915 0000:00:02.0: [drm:intel_pps_vdd_off_sync_unlocked [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
<7> [66.589404] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC off
<7> [66.589542] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [66.589841] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 00 to 02
<4> [68.628615] dmar_fault: 1343 callbacks suppressed
<3> [68.628620] DMAR: DRHD: handling fault status reg 3
<3> [68.628631] DMAR: [DMA Read NO_PASID] Request device [00:02.0] fault addr 0xfd8fb000 [fault reason 0x06] PTE Read access is not set
<3> [68.639714] DMAR: DRHD: handling fault status reg 3
<3> [68.639736] DMAR: [DMA Read NO_PASID] Request device [00:02.0] fault addr 0xfd8fb000 [fault reason 0x06] PTE Read access is not set
<3> [68.650796] DMAR: DRHD: handling fault status reg 3
<3> [68.650804] DMAR: [DMA Read NO_PASID] Request device [00:02.0] fault addr 0xfd8fb000 [fault reason 0x06] PTE Read access is not set
<3> [68.661891] DMAR: DRHD: handling fault status reg 3