- Feb 02, 2022
-
-
Tvrtko Ursulin authored
Print out end user friendly help text when the running user has insufficient privilege for accessing system wide performance counters. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Issue: https://gitlab.freedesktop.org/drm/intel/-/issues/5018 Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com>
-
- Jan 31, 2022
-
-
Swati2 Sharma authored
In this IGT, various scaling modes are validated. Scaling mode is one of the connector properties. This property defines how a non-native mode is upscaled to the native mode of an LCD panel. There are 4 types of scaling modes defined: None: No upscaling happens, scaling is left to the panel. Not all drivers expose this mode. Full: The output is upscaled to the full resolution of the panel, ignoring the aspect ratio. It will expand current image to the size of the monitor. Center: No upscaling happens, the output is centered within the native resolution the panel. As a result, black bars may appear around the image. Full aspect: The output is upscaled to maximize either the width or height while retaining the aspect ratio. It will fill the screen w/o stretching the image. Black bars are placed either on top and bottom or left and right of the picture. v2: -removed test flags/test_cycle_flags() (JP) -removed redundant igt_display_commit_atomic() (JP) -corrected indentation (JP) v3: -removed valid_test check, getting covered in igt_subtest_with_dynamic() (Bhanu) -removed redundant if statement, moved remove_fb() before skip (JP) v4: -Removed unnecessary headers (JP) -Corrected usage of igt_dynamic_f() (Bhanu) Signed-off-by:
Swati Sharma <swati2.sharma@intel.com> Reviewed-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by:
Bhanuprakash Modem <bhanuprakash.modem@intel.com>
-
- Jan 27, 2022
-
-
Ville Syrjälä authored
Currently IVB only supports 64bpp formats on the sprite planes but not on the primary plane. This means igt_display_has_format_mod(64bpp)->true and thus we will try to run the 64bpp async flip tests. But since that test uses the primary plane we will fail to actually enable the plane. Fix this by making sure the plane actually supports the format (and let's also check the rotation for good measure). Reviewed-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com>
-
- Jan 26, 2022
-
-
Juha-Pekka Heikkilä authored
On simulation it's interesting plumbing generally works and don't waste time executing long loops. Signed-off-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by:
Mika Kahola <mika.kahola@intel.com>
-
Zbigniew Kempczyński authored
Three subtests: - syncobj-timeline-chain-engines - syncobj-stationary-timeline-chain-engines - syncobj-backward-timeline-chain-engines were not previously rewritten to use no-reloc. Using allocator is not necessary in this case, we need to softpin only counter object. Offsets for all batches are chosen by the kernel as their location within gpu vm doesn't matter. Some explanation is required regarding batchbuffer updates for each iteration. Before introducing softpin all batchbuffers were touched by the relocations what introduces stalls between them during execution. These stalls could be removed as batchbuffers don't change their contents for each iteration. But I decided to keep this behavior intact for relocations changing it only for no-reloc mode. With softpinning batchbuffer for each engine is written once (for first iteration) so next execbuf reuses same batch. This removes stalls on subsequent iterations as batchbuffer for each engine is ready immediate after completion. Signed-off-by:
Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com>
-
- Jan 25, 2022
-
-
Juha-Pekka Heikkilä authored
If test fails to receive flip event within 50ms time period running test as well as all following subtests will fail. Fix actually failing test to be only one to be flagged and following subtests will not be affected by previous failure. Signed-off-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by:
Vinod Govindapillai <vinod.govindapillai@intel.com>
-
- Jan 24, 2022
-
-
When running multiple hang tests, the code is intended to disallow context ban at first, but it is always with fix ctx id 0. It will cause below test failures when running the test gem_busy: Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
Chuansheng Liu <chuansheng.liu@intel.com>
-
- Jan 21, 2022
-
-
The capture tests require knowing exactly how big the test allocation is. Part of the test is to compare the captured size against the allocated size to make sure they match. That doesn't work if the allocator creates an object of a different size than was requested without reporting the larger size. Fixes: 85a59380 ("tests/i915/gem_exec_capture: Add support for local memory") Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com>
-
- Jan 18, 2022
-
-
The test was updated some engine properties but not restoring them afterwards. That would leave the system in a non-default state which could potentially affect subsequent tests. Fix it by using the new save/restore engine properties helper functions. v2: Don't restore too soon in the 'pi' test. Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
Some platforms have very long timeouts configured for some engines. Some have them disabled completely. That makes for a very slow (or broken) hangman test. So explicitly configure the engines to have reasonable settings first. Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
Various tests want to configure engine properties such as pre-emption timeout and heartbeat interval. Some don't bother to restore the original values again afterwards. So, add a helper to make it easier to do this. v2: Fix for platforms with no pre-emption capability. Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
The update to use intel_ctx_t missed a line that configures the context to allow hanging. Fix that. Fixes: 09c36188 ("tests/i915/gem_exec_fence: Convert to intel_ctx_t (v2)") Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
The global context used by all the subtests for causing hangs is marked as unbannable. However, some of the subtests set background spinners running on all engines using a freshly created context. If there is a test failure for any reason, all of those spinners can be killed off as hanging contexts. On systems with lots of engines, that can result in the test being banned from creating any new contexts. So make the spinner contexts unbannable as well. That way if one subtest fails it won't necessarily bring down all subsequent subtests. v2: Simplify anti-banning code (review feedback from Matthew Brost). Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
As opposed to only on the non-target engines. This means that there is some other workload present for the scheduler to switch between and so detet the hang immediately. Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
The hang test was relying on context persitence for no particular reason. That is, it would set a bunch of background spinners running then immediately destroy the active contexts but expect the spinners to keep spinning. With the current implementation of context persistence in i915, that means that super high priority pings are sent to each engine at the start of the test. Depending upon the timing and platform, one of those unexpected pings could cause test failures. There is no need to require context persitence in this test. So change to managing the contexts cleanly and only destroying them when they are no longer in use. Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
Added a an extra step to the i915_hangman tests to check that the system is still alive after the hang and recovery. This submits a simple batch to each engine which does a write to memory and checks that the write occurred. v2: Use _device_coherent instead of _wc for mapping memory to support discrete boards. Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
A lot of tests use almost identical code for creating a batch buffer which does a single write to memory and another is about to be added. Instead, move the most generic version into a common helper function. Unfortunately, the other instances are all subtly different enough to make it not so trivial to try to use the helper. It could be done but it is unclear if it is worth the effort at this point. This patch proves the concept, if people like it enough then it can be extended. v2: Fix up object address vs store offset confusion (with help from Zbigniew K). v3: Cope with >32bit store_offset (review feedback from Matthew Brost). Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
The hangman framework sets up a context that is valid for all engines and has things like banning disabled. The 'unterminated' test then ignores it and uses the default context. Fix that. Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
Some of the IGT framework relies on receving a uevent when a hang occurs. So add a test that this actually works. While testing this, noticed that hangs could sometimes be missed because the uevent was (presumably) still in flight by the time the handler was de-registered. So add an extra delay during cleanup to give the uevent chance to arrive. Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
Although the hangman test was ensuring that *some* reset functionality was enabled, it did not differentiate what kind. The infrastructure required to choose between per engine reset or full GT reset was recently added. So update this test to use it as well. Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
The capture test was still using old style ring_id and ring_name (derived from the engine structure at the higher level). Update it to just take the engine structure directly. Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
The above function was checking for valid rings via the old interface. The new scheme is to check for engines on contexts as there are now more engines than could be supported. Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com>
-
Added descriptions of the various sub-tests and the test as a whole. v2: Added missing linefeed (spotted by Petri) Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Petri Latvala <petri.latvala@intel.com>
-
Igt_fixture is in a loop for different operations. This is causing display_fini being called at the end of each iteration and triggering SIGSEGV. Fix this by removing igt_fixture out from the loop. Fixes: 6be8feeb ("tests/kms_psr2_su: add biplanar selective update tests") Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com>
-
- Jan 15, 2022
-
-
DRM_IOCTL_I915_GEM_SET_DOMAIN ioctl is not supported on discrete platforms. Skip sd-probe test for discrete platforms. https://patchwork.freedesktop.org/patch/msgid/20210715101536.2606307-5-matthew.auld@intel.com v2: add a newline at the end of the skip string and fix the skip string. (Petri) v3: update the commit message. (Petri) Cc: Matthew Auld <matthew.auld@intel.com> Cc: Petri Latvala <petri.latvala@intel.com> Signed-off-by:
Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Reviewed-by:
Matthew Auld <matthew.auld@intel.com> Reviewed-by:
Petri Latvala <petri.latvala@intel.com>
-
- Jan 10, 2022
-
-
Zbigniew Kempczyński authored
This test takes up to few hundred of milliseconds and exercises detecting of safe starting offset and alignment to use on discrete where memory regions constraints could differ on different gens. Signed-off-by:
Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Cc: Petri Latvala <petri.latvala@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Acked-by:
Petri Latvala <petri.latvala@intel.com>
-
Zbigniew Kempczyński authored
Exercise start offset and alignment detection when we start mixing system and local memory. v2: support integrated and check smem <-> smem alignment v3: iterate over engines to verify safe start is correct everywhere v4: rename to safe-alignment (Ashutosh) Signed-off-by:
Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Cc: Petri Latvala <petri.latvala@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com>
-
Zbigniew Kempczyński authored
With era of new gens we're enforced to use no-reloc (softpin). This brings few problems like vm range limitations which were well solved by the kernel. This can be handled also in userspace code by adding gen related conditionals or by trying to detect the constraints. Lets try to do this dynamically and detect safe start offset and alignment for each memory region we got. This should be universal solution regardless hw limitations and bugs. As such detection is not lightweight technique add also some caching structures to handle consequtive calls about same data. v2: unify cache v3: move allocation of cache entry out of mutex v4: remove assert on allocation newentry, just skip adding to cache v5: fix function documentation (Ashutosh) v6: remove unnecessary buffers count initialization (Ashutosh) add 48b flag for pinning object Signed-off-by:
Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Cc: Petri Latvala <petri.latvala@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com>
-
- Jan 06, 2022
-
-
Commit d7a74b95 ("tests/i915/perf_pmu: Convert to intel_ctx_t (v3)") broke the test when it is run in its entirety. Correct context id needs to be used with igt_allow_hang to avoid context ban preventing the test to run to completion. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Fixes: d7a74b95 ("tests/i915/perf_pmu: Convert to intel_ctx_t (v3)") Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com>
-
We need to use the FIXED mapping type on discrete platforms. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Priyanka Dandamudi <priyanka.dandamudi@intel.com> Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com>
-
- Jan 04, 2022
-
-
Media samplers are not present on some of Gen11 platforms adding skip on EHL and JSL as per Bspec. Bspec:29151 Changes since V1 : Moved this skip check to igt_get_media_vme_func.[Tony Ye] CC: Tony Ye <tony.ye@intel.com> Signed-off-by:
Mastan Katragadda <mastanx.katragadda@intel.com> Reviewed-by:
Tony Ye <tony.ye@intel.com>
-
- Dec 30, 2021
-
-
P010 pixel format is newly added to the already existing list of pixel formats(RGB565,XRGB8888,NV12). Signed-off-by:
Ananya Sharma <ananya.sharma@intel.com> Reviewed-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
-
- Dec 27, 2021
-
-
Add support for local memory region (Device memory) Signed-off-by:
Ch Sai Gowtham <sai.gowtham.ch@intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Reviewed-by:
Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
-
RPLS and ADLS use the same OA metrics. Add RPLS support for OA tests. Resolves: https://gitlab.freedesktop.org/drm/intel/-/issues/4808 Signed-off-by:
Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Acked-by:
Ashutosh Dixit <ashutosh.dixit@intel.com>
-
- Dec 23, 2021
-
-
Bhanuprakash Modem authored
Instead of iterating through all the delta, break the execution when we found a match. This will optimize the time required to execute ctm-0-* tests. Cc: Karthik B S <karthik.b.s@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by:
Bhanuprakash Modem <bhanuprakash.modem@intel.com> Reviewed-by:
Karthik B S <karthik.b.s@intel.com>
-
Juha-Pekka Heikkilä authored
Create reference crc with same modifier as is used for testing. This will reduce non test related anomalies. Signed-off-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com>
-
- Dec 22, 2021
-
-
Swati2 Sharma authored
In this patch, added upscaling tests 960x540->1920x1080. Existing downscaled tests reused for upscaling scenarios. Signed-off-by:
Swati Sharma <swati2.sharma@intel.com> Reviewed-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
-
Swati2 Sharma authored
Signed-off-by:
Swati Sharma <swati2.sharma@intel.com> Reviewed-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
-
- Dec 21, 2021
-
-
Eryk Brol authored
This commit adds a DP DSC test that checks: * Forces DSC on/off and ensures it is reset properly * Check DSC slice height property * Verify various DSC slice dimensions * Tests various combinations of link_rate + lane_count and logs if DSC enabled/disabled Tests different bpc settings and logs if DSC is enabled/disabled Change since V3: - Drop useless test Change since V2: - Remove IGT_CRTC_DSC_SLICE_HEIGHT crtc property from this commit Change since V1: - Rebase Cc: Harry Wentland <harry.wentland@amd.com> Cc: Nicholas Choi <Nicholas.Choi@amd.com> Cc: Mark Yacoub <markyacoub@chromium.org> Cc: Hayden Goodfellow <hayden.goodfellow@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Roman Li <roman.li@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
Eryk Brol <eryk.brol@amd.com>
-
Tejas Upadhyay authored
Adding Alder lake N platform definitions Reviewed-by:
Petri Latvala <petri.latvala@intel.com> Signed-off-by:
Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
-