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Juha-Pekka Heikkilä authored
starting pipe crc causes modeset on psr panels which take lot of time. Fix this by starting crc only in the beginning and stop at the end of test. Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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