igt@kms_plane_multiple@tiling-x@pipe-d-dp-3 - skip - Test requirement not met in function get_reference_crc, Test requirement: !(ret != 0), Last errno: 22
https://gfx-ci.igk.intel.com/cibuglog-ng/testresult/1759339705?query_key=ac9abe700c3948b52ae7852b65818a96f8a49ba3
Stdout
Starting dynamic subtest: pipe-D-DP-3
Using (pipe D + DP-3) to run the subtest.
Test requirement not met in function get_reference_crc, file ../../../usr/src/igt-gpu-tools/tests/kms_plane_multiple.c:153:
Test requirement: !(ret != 0)
Last errno: 22, Invalid argument
Dynamic subtest pipe-D-DP-3: SKIP (0.060s)
Subtest tiling-x: FAIL (4.621s)
Stderr
Starting dynamic subtest: pipe-D-DP-3
Dynamic subtest pipe-D-DP-3: SKIP (0.060s)
Subtest tiling-x: FAIL (4.621s)
Dmesg
<6> [145.303250] [IGT] kms_plane_multiple: starting dynamic subtest pipe-D-DP-3
<7> [145.304824] i915 0000:00:02.0: [drm:intel_dpt_create [i915]] Allocating dpt from smem
<7> [145.305251] i915 0000:00:02.0: [drm:drm_mode_addfb2] [FB:293]
<7> [145.312742] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling always-on
<7> [145.313778] [drm:eb_lookup_vmas [i915]] EINVAL at eb_validate_vma:510
<7> [145.314703] [drm:eb_lookup_vmas [i915]] EINVAL at eb_validate_vma:510
<7> [145.345606] [drm:eb_lookup_vmas [i915]] EINVAL at eb_validate_vma:510
<7> [145.346118] [drm:eb_lookup_vmas [i915]] EINVAL at eb_validate_vma:510
<7> [145.360318] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:264:DP-3] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
<7> [145.360662] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:263:DDI TC3/PHY TC3][CRTC:238:pipe D] DP link limits: pixel clock 533250 kHz DSC off max lanes 4 max rate 270000 max pipe_bpp 30 max link_bpp 30.0000
<7> [145.360931] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] Try DSC (fallback=yes, joiner=no, force=no)
<7> [145.361199] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:263:DDI TC3/PHY TC3][CRTC:238:pipe D] DP link limits: pixel clock 533250 kHz DSC on max lanes 4 max rate 270000 max pipe_bpp 30 max link_bpp 30.0000
<7> [145.361463] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:263:DDI TC3/PHY TC3][CRTC:238:pipe D] DP link limits: pixel clock 533250 kHz DSC off max lanes 4 max rate 270000 max pipe_bpp 30 max link_bpp 30.0000
<7> [145.361704] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] Try DSC (fallback=yes, joiner=no, force=no)
<7> [145.361939] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:263:DDI TC3/PHY TC3][CRTC:238:pipe D] DP link limits: pixel clock 533250 kHz DSC on max lanes 4 max rate 270000 max pipe_bpp 30 max link_bpp 30.0000
<7> [145.362193] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [ENCODER:263:DDI TC3/PHY TC3] config failure: -22
<7> [145.362481] i915 0000:00:02.0: [drm] [CRTC:82:pipe A] enable: no [failed]
<7> [145.362487] i915 0000:00:02.0: [drm] [PLANE:32:plane 1A] fb: [NOFB], visible: no
<7> [145.362491] i915 0000:00:02.0: [drm] [PLANE:41:plane 2A] fb: [NOFB], visible: no
<7> [145.362495] i915 0000:00:02.0: [drm] [PLANE:50:plane 3A] fb: [NOFB], visible: no
<7> [145.362498] i915 0000:00:02.0: [drm] [PLANE:59:plane 4A] fb: [NOFB], visible: no
<7> [145.362502] i915 0000:00:02.0: [drm] [PLANE:68:plane 5A] fb: [NOFB], visible: no
<7> [145.362506] i915 0000:00:02.0: [drm] [PLANE:77:cursor A] fb: [NOFB], visible: no
<7> [145.362509] i915 0000:00:02.0: [drm] [CRTC:134:pipe B] enable: no [failed]
<7> [145.362513] i915 0000:00:02.0: [drm] [PLANE:84:plane 1B] fb: [NOFB], visible: no
<7> [145.362517] i915 0000:00:02.0: [drm] [PLANE:93:plane 2B] fb: [NOFB], visible: no
<7> [145.362520] i915 0000:00:02.0: [drm] [PLANE:102:plane 3B] fb: [NOFB], visible: no