<6> [26.570369] [IGT] kms_cursor_crc: starting subtest pipe-A-cursor-256x85-sliding
<7> [26.570841] [drm:drm_mode_addfb2] [FB:334]
<7> [26.580684] [drm:drm_mode_addfb2] [FB:335]
<7> [26.627769] [drm:drm_mode_setcrtc] [CRTC:91:pipe A]
<7> [26.627834] [drm:drm_mode_setcrtc] [CONNECTOR:276:eDP-1]
<7> [26.641582] [drm:drm_mode_setcrtc] [CRTC:152:pipe B]
<7> [26.644777] [drm:drm_mode_setcrtc] [CRTC:213:pipe C]
<7> [26.647888] [drm:drm_mode_setcrtc] [CRTC:274:pipe D]
<7> [26.650881] [drm:intel_atomic_check [i915]] [CONNECTOR:276:eDP-1] Limiting display bpp to 18 instead of EDID bpp 18, requested bpp 36, max platform bpp 36
<7> [26.650938] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max rate 270000 max bpp 18 pixel clock 214000KHz
<7> [26.650975] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [26.651012] [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 270000 bpp 18
<7> [26.651047] [drm:intel_dp_compute_config [i915]] DP link rate required 481500 available 540000
<7> [26.651081] [drm:intel_ddi_compute_config [i915]] DC3CO exit scanlines 1058
<7> [26.651119] [drm:intel_atomic_check [i915]] hw max bpp: 18, pipe bpp: 18, dithering: 1
<7> [26.651173] [drm:intel_dump_pipe_config [i915]] [CRTC:91:pipe A] enable: yes [fastset]
<7> [26.651212] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [26.651249] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 18, dithering: 1
<7> [26.651283] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 7479842, gmch_n: 8388608, link_m: 415546, link_n: 524288, tu: 64
<7> [26.651320] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0
<7> [26.651356] [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [26.651360] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 90 214000 1920 1936 1952 2104 1080 1083 1097 1128 0x48 0xa
<7> [26.651407] [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [26.651411] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 90 214000 1920 1936 1952 2104 1080 1083 1097 1128 0x48 0xa
<7> [26.651456] [drm:intel_dump_pipe_config [i915]] crtc timings: 214000 1920 1936 1952 2104 1080 1083 1097 1128, type: 0x48 flags: 0xa
<7> [26.651491] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 214000
<7> [26.651526] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [26.651567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no
<7> [26.651694] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [26.651756] [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x1c001a5, cfgcr1: 0x88, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0
<7> [26.651799] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [26.651849] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [26.651896] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:334] 1920x1080 format = XR24 little-endian (0x34325258), visible: yes
<7> [26.651943] [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [26.651989] [drm:intel_dump_pipe_config [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0
<7> [26.652513] [drm:intel_ddi_update_pipe [i915]] Panel doesn't support DRRS
<7> [26.661148] [drm:verify_connector_state [i915]] [CONNECTOR:276:eDP-1]
<7> [26.661244] [drm:intel_atomic_commit_tail [i915]] [CRTC:91:pipe A]
<7> [26.661431] [drm:intel_ddi_get_config [i915]] [ENCODER:275:DDI A] Fec status: 0
<7> [26.661491] [drm:verify_single_dpll_state.isra.149 [i915]] DPLL 0
<7> [26.662714] [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe A
<7> [26.731831] [drm:tgl_dc5_idle_thread [i915]] DC5/6 idle thread
<7> [26.739370] [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe A
<7> [26.739596] [drm:intel_atomic_check [i915]] [CONNECTOR:276:eDP-1] Limiting display bpp to 18 instead of EDID bpp 18, requested bpp 36, max platform bpp 36
<7> [26.739835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max rate 270000 max bpp 18 pixel clock 214000KHz
<7> [26.739880] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [26.739931] [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 270000 bpp 18
<7> [26.739979] [drm:intel_dp_compute_config [i915]] DP link rate required 481500 available 540000
<7> [26.740028] [drm:intel_psr_compute_config [i915]] PSR2 not enabled because it would inhibit pipe CRC calculation
<7> [26.740076] [drm:intel_atomic_check [i915]] hw max bpp: 18, pipe bpp: 18, dithering: 1
<7> [26.740126] [drm:pipe_config_mismatch [i915]] [CRTC:91:pipe A] fastset mismatch in dc3co_exitline (expected 1058, found 0)
<7> [26.740199] [drm:intel_find_shared_dpll [i915]] [CRTC:91:pipe A] allocated DPLL 0
<7> [26.740246] [drm:intel_reference_shared_dpll.isra.11 [i915]] using DPLL 0 for pipe A
<7> [26.740396] [drm:intel_dump_pipe_config [i915]] [CRTC:91:pipe A] enable: yes [modeset]
<7> [26.740446] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [26.740510] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 18, dithering: 1
<7> [26.740558] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 7479842, gmch_n: 8388608, link_m: 415546, link_n: 524288, tu: 64
<7> [26.740641] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0
<7> [26.740690] [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [26.740697] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 90 214000 1920 1936 1952 2104 1080 1083 1097 1128 0x48 0xa
<7> [26.740751] [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [26.740758] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 90 214000 1920 1936 1952 2104 1080 1083 1097 1128 0x48 0xa
<7> [26.740807] [drm:intel_dump_pipe_config [i915]] crtc timings: 214000 1920 1936 1952 2104 1080 1083 1097 1128, type: 0x48 flags: 0xa
<7> [26.740853] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 214000
<7> [26.740896] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [26.740940] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no
<7> [26.740984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [26.741032] [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x1c001a5, cfgcr1: 0x88, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0
<7> [26.741076] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [26.741120] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [26.741165] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:334] 1920x1080 format = XR24 little-endian (0x34325258), visible: yes
<7> [26.741208] [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [26.741253] [drm:intel_dump_pipe_config [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0
<7> [26.741296] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2A] fb: [NOFB], visible: no
<7> [26.741339] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 3A] fb: [NOFB], visible: no
<7> [26.741383] [drm:intel_dump_pipe_config [i915]] [PLANE:55:plane 4A] fb: [NOFB], visible: no
<7> [26.741428] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 5A] fb: [NOFB], visible: no
<7> [26.741488] [drm:intel_dump_pipe_config [i915]] [PLANE:71:plane 6A] fb: [NOFB], visible: no
<7> [26.741532] [drm:intel_dump_pipe_config [i915]] [PLANE:79:plane 7A] fb: [NOFB], visible: no
<7> [26.741579] [drm:intel_dump_pipe_config [i915]] [PLANE:87:cursor A] fb: [NOFB], visible: no
<7> [26.744581] [drm:intel_psr_disable_locked [i915]] Disabling PSR2
<7> [26.754154] [drm:intel_edp_backlight_off [i915]]
<7> [26.955678] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
<7> [26.955910] [drm:intel_disable_pipe [i915]] disabling pipe A
<7> [26.964330] [drm:intel_edp_panel_off.part.52 [i915]] Turn [ENCODER:275:DDI A] panel power off
<7> [26.964506] [drm:intel_edp_panel_off.part.52 [i915]] Wait for panel power off time
<7> [26.964783] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
<7> [27.017530] [drm:wait_panel_status [i915]] Wait complete
<7> [27.017735] [drm:intel_power_well_disable [i915]] disabling DDI A IO
<7> [27.017973] [drm:intel_power_well_disable [i915]] disabling AUX A
<7> [27.018104] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
<7> [27.018231] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 91
<7> [27.018377] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
<7> [27.018504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:275:DDI A]
<7> [27.018620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:282:DDI B]
<7> [27.018756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:284:DP-MST A]
<7> [27.018866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:285:DP-MST B]
<7> [27.018958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:286:DP-MST C]
<7> [27.019070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:287:DP-MST D]
<7> [27.019165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:298:DDI D]
<7> [27.019278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:300:DP-MST A]
<7> [27.019373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:301:DP-MST B]
<7> [27.019477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:302:DP-MST C]
<7> [27.019586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:303:DP-MST D]
<7> [27.019704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:306:DDI E]
<7> [27.019813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:308:DP-MST A]
<7> [27.019901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:309:DP-MST B]
<7> [27.020000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:310:DP-MST C]
<7> [27.020142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:311:DP-MST D]
<7> [27.020225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:314:DDI F]
<7> [27.020315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:316:DP-MST A]
<7> [27.020405] [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x00010000, dig 0x0000088a, pins 0x00000010, long 0x00000010
<7> [27.020496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:317:DP-MST B]
<7> [27.020623] [drm:intel_hpd_irq_handler [i915]] digital hpd on [ENCODER:275:DDI A] - long
<7> [27.020717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:318:DP-MST C]
<7> [27.020837] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 10
<7> [27.020930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:319:DP-MST D]
<7> [27.021102] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP [ENCODER:275:DDI A]
<7> [27.021204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:322:DDI G]
<7> [27.021294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:324:DP-MST A]
<7> [27.021398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:325:DP-MST B]
<7> [27.021500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:326:DP-MST C]
<7> [27.021604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:327:DP-MST D]
<7> [27.021733] [drm:verify_single_dpll_state.isra.149 [i915]] DPLL 0
<7> [27.021858] [drm:verify_single_dpll_state.isra.149 [i915]] DPLL 1
<7> [27.021983] [drm:verify_single_dpll_state.isra.149 [i915]] TBT PLL
<7> [27.022105] [drm:verify_single_dpll_state.isra.149 [i915]] TC PLL 1
<7> [27.022230] [drm:verify_single_dpll_state.isra.149 [i915]] TC PLL 2
<7> [27.022352] [drm:verify_single_dpll_state.isra.149 [i915]] TC PLL 3
<7> [27.022478] [drm:verify_single_dpll_state.isra.149 [i915]] TC PLL 4
<7> [27.022603] [drm:verify_single_dpll_state.isra.149 [i915]] TC PLL 5
<7> [27.022748] [drm:verify_single_dpll_state.isra.149 [i915]] TC PLL 6
<7> [27.022863] [drm:intel_power_well_enable [i915]] enabling AUX A
<7> [27.022964] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 91
<7> [27.023065] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
<7> [27.023215] [drm:edp_panel_on [i915]] Turn [ENCODER:275:DDI A] panel power on
<7> [27.023341] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
<7> [27.675904] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
<7> [27.676035] [drm:wait_panel_status [i915]] Wait complete
<7> [27.676218] [drm:edp_panel_on [i915]] Wait for panel power on
<7> [27.676459] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
<7> [27.744464] [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x00010000, dig 0x0000088a, pins 0x00000010, long 0x00000010
<7> [27.744591] [drm:intel_hpd_irq_handler [i915]] digital hpd on [ENCODER:275:DDI A] - long
<7> [27.744710] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 20
<7> [27.744891] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP [ENCODER:275:DDI A]
<0> [27.803866] BUG: stack guard page was hit at 0000000038f7e63a (stack is 00000000dfcb8a9b..0000000036426b96)