Overlay plane alpha channel blending is incorrect
Brief summary of the problem:
Setup KMS to scanout a solid green buffer on the primary plane and the following image on the overlay plane:
Expected result:
Actual output:
Even if the alpha in the gradient is linear, the hw has some sort of cut-out value: below a certain threshold pixels are completely transparent even though they have alpha != 0.
Hardware description:
- CPU: Zen 2
- GPU: 04:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] VanGogh (rev ae)
- System Memory: N/A
- Display(s): N/A
- Type of Display Connection: eDP
System information:
- Distro name and Version: ArchLinux
- Kernel version: 5.13.0
- Custom kernel: agd5f/amd-staging-drm-next
- AMD package version: N/A
How to reproduce the issue:
Run tentative with the following config (may need to tweak the CRTC/plane IDs for your system):
# primary
plane 55 {
CRTC_ID crtc 68
CRTC_X value 0
CRTC_Y value 0
FB_ID fb {
size 800x1280
fill_color "#00FF00"
}
}
# overlay
plane 60 {
CRTC_ID crtc 68
CRTC_X value 100
CRTC_Y value 200
CRTC_W value 256
CRTC_H value 256
SRC_X value 0
SRC_Y value 0
SRC_W value 256
SRC_H value 256
FB_ID fb {
size 256x256
fill_file gradient.ARGB8888-256x256.raw
format ARGB8888
}
}Raw buffer used for the overlay: gradient.ARGB8888-256x256.raw (obtained with: contrib/drm-convert /path/to//gradient.png ARGB8888 run in the tentative source dir)
Activity
added DC label
Can you clarify some of the elements that are missing from the commit state you posted?
Overlay
pixel_blend_mode= ? (DRM_MODE_BLEND_PREMULTI?)alpha= ? (0xffff?)CRTC
GAMMA_LUT= ? (NULL?)DEGAMMA_LUT= ? (NULL?)CTM= ? (NULL?)This is to help understand what parts of the color pipeline are enabled. I had previously worked on getting a pass on
kms_plane_alpha_blendtests in IGT before but something may have regressed since then.Ideally the entire color pipeline will be in bypass so only the blender HW state (MPCC) needs investigation. In particular the MPCC_CONTROL[0].MPCC_ALPHA_BLND_MODE / MPCC_CONTROL[0].MPCC_ALPHA_MULTIPLIED_MODE fields are relevant here.
The brief at the top of
amdgpu_dm_color.cgives a bit of an introduction to how the pipeline works on a general level (for DCN1) but for a more complete picture you could take a read at some of the HDR color RFC discussion that Harry has been involved with on dri-devel recently.Edited by Nicholas KazlauskasOverlay
pixel_blend_mode= ? (DRM_MODE_BLEND_PREMULTI?)alpha= ? (0xffff?)CRTC
GAMMA_LUT= ? (NULL?)DEGAMMA_LUT= ? (NULL?)CTM= ? (NULL?)Yes for all of the above. Full
drm_infolog:Node: /dev/dri/card0 ├───Driver: amdgpu (AMD GPU) version 3.44.0 (20150101) │ ├───DRM_CLIENT_CAP_STEREO_3D supported │ ├───DRM_CLIENT_CAP_UNIVERSAL_PLANES supported │ ├───DRM_CLIENT_CAP_ATOMIC supported │ ├───DRM_CLIENT_CAP_ASPECT_RATIO supported │ ├───DRM_CLIENT_CAP_WRITEBACK_CONNECTORS supported │ ├───DRM_CAP_DUMB_BUFFER = 1 │ ├───DRM_CAP_VBLANK_HIGH_CRTC = 1 │ ├───DRM_CAP_DUMB_PREFERRED_DEPTH = 24 │ ├───DRM_CAP_DUMB_PREFER_SHADOW = 1 │ ├───DRM_CAP_PRIME = 3 │ ├───DRM_CAP_TIMESTAMP_MONOTONIC = 1 │ ├───DRM_CAP_ASYNC_PAGE_FLIP = 1 │ ├───DRM_CAP_CURSOR_WIDTH = 256 │ ├───DRM_CAP_CURSOR_HEIGHT = 256 │ ├───DRM_CAP_ADDFB2_MODIFIERS = 1 │ ├───DRM_CAP_PAGE_FLIP_TARGET = 0 │ ├───DRM_CAP_CRTC_IN_VBLANK_EVENT = 1 │ ├───DRM_CAP_SYNCOBJ = 1 │ └───DRM_CAP_SYNCOBJ_TIMELINE = 1 ├───Device: PCI 1002:163f │ └───Available nodes: primary, render ├───Framebuffer size │ ├───Width: [0, 16384] │ └───Height: [0, 16384] ├───Connectors │ ├───Connector 0 │ │ ├───Object ID: 82 │ │ ├───Type: eDP │ │ ├───Status: connected │ │ ├───Physical size: 60x50 mm │ │ ├───Subpixel: unknown │ │ ├───Encoders: {0} │ │ ├───Modes │ │ │ ├───800x1280@59.99 preferred driver phsync pvsync │ │ │ ├───800x600@59.99 driver phsync pvsync │ │ │ ├───640x480@59.99 driver phsync pvsync │ │ │ └───256x160@58.79 nhsync pvsync │ │ └───Properties │ │ ├───"EDID" (immutable): blob = 88 │ │ ├───"DPMS": enum {On, Standby, Suspend, Off} = On │ │ ├───"link-status": enum {Good, Bad} = Good │ │ ├───"non-desktop" (immutable): range [0, 1] = 0 │ │ ├───"TILE" (immutable): blob = 0 │ │ ├───"CRTC_ID" (atomic): object CRTC = 68 │ │ ├───"scaling mode": enum {None, Full, Center, Full aspect} = None │ │ ├───"underscan": enum {off, on, auto} = off │ │ ├───"underscan hborder": range [0, 128] = 0 │ │ ├───"underscan vborder": range [0, 128] = 0 │ │ ├───"max bpc": range [8, 16] = 16 │ │ ├───"abm level": range [0, 4] = 0 │ │ ├───"HDR_OUTPUT_METADATA": blob = 0 │ │ ├───"vrr_capable" (immutable): range [0, 1] = 0 │ │ ├───"Content Protection": enum {Undesired, Desired, Enabled} = Undesired │ │ └───"HDCP Content Type": enum {HDCP Type0, HDCP Type1} = HDCP Type0 │ └───Connector 1 │ ├───Object ID: 89 │ ├───Type: DisplayPort │ ├───Status: disconnected │ ├───Encoders: {1} │ └───Properties │ ├───"EDID" (immutable): blob = 0 │ ├───"DPMS": enum {On, Standby, Suspend, Off} = Off │ ├───"link-status": enum {Good, Bad} = Good │ ├───"non-desktop" (immutable): range [0, 1] = 0 │ ├───"TILE" (immutable): blob = 0 │ ├───"CRTC_ID" (atomic): object CRTC = 0 │ ├───"scaling mode": enum {None, Full, Center, Full aspect} = None │ ├───"underscan": enum {off, on, auto} = off │ ├───"underscan hborder": range [0, 128] = 0 │ ├───"underscan vborder": range [0, 128] = 0 │ ├───"max bpc": range [8, 16] = 8 │ ├───"HDR_OUTPUT_METADATA": blob = 0 │ ├───"vrr_capable" (immutable): range [0, 1] = 0 │ ├───"Content Protection": enum {Undesired, Desired, Enabled} = Undesired │ ├───"HDCP Content Type": enum {HDCP Type0, HDCP Type1} = HDCP Type0 │ └───"subconnector" (immutable): enum {Unknown, VGA, DVI-D, HDMI, DP, Wireless, Native} = Unknown ├───Encoders │ ├───Encoder 0 │ │ ├───Object ID: 81 │ │ ├───Type: TMDS │ │ ├───CRTCS: {0, 1, 2, 3} │ │ └───Clones: {0} │ ├───Encoder 1 │ │ ├───Object ID: 87 │ │ ├───Type: TMDS │ │ ├───CRTCS: {0, 1, 2, 3} │ │ └───Clones: {1} │ ├───Encoder 2 │ │ ├───Object ID: 93 │ │ ├───Type: DP MST │ │ ├───CRTCS: {0, 1, 2, 3} │ │ └───Clones: {2} │ ├───Encoder 3 │ │ ├───Object ID: 94 │ │ ├───Type: DP MST │ │ ├───CRTCS: {0, 1, 2, 3} │ │ └───Clones: {3} │ ├───Encoder 4 │ │ ├───Object ID: 95 │ │ ├───Type: DP MST │ │ ├───CRTCS: {0, 1, 2, 3} │ │ └───Clones: {4} │ └───Encoder 5 │ ├───Object ID: 96 │ ├───Type: DP MST │ ├───CRTCS: {0, 1, 2, 3} │ └───Clones: {5} ├───CRTCs │ ├───CRTC 0 │ │ ├───Object ID: 68 │ │ ├───Mode: 800x1280@59.99 preferred driver phsync pvsync │ │ ├───Gamma size: 256 │ │ └───Properties │ │ ├───"ACTIVE" (atomic): range [0, 1] = 1 │ │ ├───"MODE_ID" (atomic): blob = 98 │ │ │ └───800x1280@59.99 preferred driver phsync pvsync │ │ ├───"OUT_FENCE_PTR" (atomic): range [0, UINT64_MAX] = 0 │ │ ├───"VRR_ENABLED": range [0, 1] = 0 │ │ ├───"DEGAMMA_LUT": blob = 0 │ │ ├───"DEGAMMA_LUT_SIZE" (immutable): range [0, UINT32_MAX] = 4096 │ │ ├───"CTM": blob = 0 │ │ ├───"GAMMA_LUT": blob = 0 │ │ └───"GAMMA_LUT_SIZE" (immutable): range [0, UINT32_MAX] = 4096 │ ├───CRTC 1 │ │ ├───Object ID: 72 │ │ ├───Gamma size: 256 │ │ └───Properties │ │ ├───"ACTIVE" (atomic): range [0, 1] = 0 │ │ ├───"MODE_ID" (atomic): blob = 0 │ │ ├───"OUT_FENCE_PTR" (atomic): range [0, UINT64_MAX] = 0 │ │ ├───"VRR_ENABLED": range [0, 1] = 0 │ │ ├───"DEGAMMA_LUT": blob = 0 │ │ ├───"DEGAMMA_LUT_SIZE" (immutable): range [0, UINT32_MAX] = 4096 │ │ ├───"CTM": blob = 0 │ │ ├───"GAMMA_LUT": blob = 0 │ │ └───"GAMMA_LUT_SIZE" (immutable): range [0, UINT32_MAX] = 4096 │ ├───CRTC 2 │ │ ├───Object ID: 76 │ │ ├───Gamma size: 256 │ │ └───Properties │ │ ├───"ACTIVE" (atomic): range [0, 1] = 0 │ │ ├───"MODE_ID" (atomic): blob = 0 │ │ ├───"OUT_FENCE_PTR" (atomic): range [0, UINT64_MAX] = 0 │ │ ├───"VRR_ENABLED": range [0, 1] = 0 │ │ ├───"DEGAMMA_LUT": blob = 0 │ │ ├───"DEGAMMA_LUT_SIZE" (immutable): range [0, UINT32_MAX] = 4096 │ │ ├───"CTM": blob = 0 │ │ ├───"GAMMA_LUT": blob = 0 │ │ └───"GAMMA_LUT_SIZE" (immutable): range [0, UINT32_MAX] = 4096 │ └───CRTC 3 │ ├───Object ID: 80 │ ├───Gamma size: 256 │ └───Properties │ ├───"ACTIVE" (atomic): range [0, 1] = 0 │ ├───"MODE_ID" (atomic): blob = 0 │ ├───"OUT_FENCE_PTR" (atomic): range [0, UINT64_MAX] = 0 │ ├───"VRR_ENABLED": range [0, 1] = 0 │ ├───"DEGAMMA_LUT": blob = 0 │ ├───"DEGAMMA_LUT_SIZE" (immutable): range [0, UINT32_MAX] = 4096 │ ├───"CTM": blob = 0 │ ├───"GAMMA_LUT": blob = 0 │ └───"GAMMA_LUT_SIZE" (immutable): range [0, UINT32_MAX] = 4096 └───Planes ├───Plane 0 │ ├───Object ID: 40 │ ├───CRTCs: {3} │ ├───FB ID: 0 │ ├───Formats: │ │ ├───XRGB8888 (0x34325258) │ │ ├───ARGB8888 (0x34325241) │ │ ├───RGBA8888 (0x34324152) │ │ ├───XRGB2101010 (0x30335258) │ │ ├───XBGR2101010 (0x30334258) │ │ ├───ARGB2101010 (0x30335241) │ │ ├───ABGR2101010 (0x30334241) │ │ ├───Unknown (0x38345258) │ │ ├───Unknown (0x38344258) │ │ ├───Unknown (0x38345241) │ │ ├───Unknown (0x38344241) │ │ ├───XBGR8888 (0x34324258) │ │ ├───ABGR8888 (0x34324241) │ │ ├───RGB565 (0x36314752) │ │ ├───NV12 (0x3231564e) │ │ ├───XRGB16161616F (0x48345258) │ │ ├───ARGB16161616F (0x48345241) │ │ ├───XBGR16161616F (0x48344258) │ │ └───ABGR16161616F (0x48344241) │ └───Properties │ ├───"type" (immutable): enum {Overlay, Primary, Cursor} = Primary │ ├───"FB_ID" (atomic): object framebuffer = 0 │ ├───"IN_FENCE_FD" (atomic): srange [-1, INT32_MAX] = -1 │ ├───"CRTC_ID" (atomic): object CRTC = 0 │ ├───"CRTC_X" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_Y" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_W" (atomic): range [0, INT32_MAX] = 0 │ ├───"CRTC_H" (atomic): range [0, INT32_MAX] = 0 │ ├───"SRC_X" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_Y" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_W" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_H" (atomic): range [0, UINT32_MAX] = 0 │ ├───"IN_FORMATS" (immutable): blob = 41 │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008533b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008563b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008537b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008567b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008401b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ ├───RGB565 (0x36314752) │ │ │ ├───NV12 (0x3231564e) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008401903) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ ├───RGB565 (0x36314752) │ │ │ ├───NV12 (0x3231564e) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ ├───AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) (0x200000000000a01) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ ├───AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) (0x200000000000901) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ ├───RGB565 (0x36314752) │ │ │ ├───NV12 (0x3231564e) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ └───DRM_FORMAT_MOD_LINEAR (0x0) │ │ ├───XRGB8888 (0x34325258) │ │ ├───ARGB8888 (0x34325241) │ │ ├───RGBA8888 (0x34324152) │ │ ├───XRGB2101010 (0x30335258) │ │ ├───XBGR2101010 (0x30334258) │ │ ├───ARGB2101010 (0x30335241) │ │ ├───ABGR2101010 (0x30334241) │ │ ├───Unknown (0x38345258) │ │ ├───Unknown (0x38344258) │ │ ├───Unknown (0x38345241) │ │ ├───Unknown (0x38344241) │ │ ├───XBGR8888 (0x34324258) │ │ ├───ABGR8888 (0x34324241) │ │ ├───RGB565 (0x36314752) │ │ ├───NV12 (0x3231564e) │ │ ├───XRGB16161616F (0x48345258) │ │ ├───ARGB16161616F (0x48345241) │ │ ├───XBGR16161616F (0x48344258) │ │ └───ABGR16161616F (0x48344241) │ ├───"COLOR_ENCODING": enum {ITU-R BT.601 YCbCr, ITU-R BT.709 YCbCr, ITU-R BT.2020 YCbCr} = ITU-R BT.601 YCbCr │ ├───"COLOR_RANGE": enum {YCbCr limited range, YCbCr full range} = YCbCr limited range │ └───"rotation": bitmask {rotate-0, rotate-90, rotate-180, rotate-270} = (rotate-0) ├───Plane 1 │ ├───Object ID: 45 │ ├───CRTCs: {2} │ ├───FB ID: 0 │ ├───Formats: │ │ ├───XRGB8888 (0x34325258) │ │ ├───ARGB8888 (0x34325241) │ │ ├───RGBA8888 (0x34324152) │ │ ├───XRGB2101010 (0x30335258) │ │ ├───XBGR2101010 (0x30334258) │ │ ├───ARGB2101010 (0x30335241) │ │ ├───ABGR2101010 (0x30334241) │ │ ├───Unknown (0x38345258) │ │ ├───Unknown (0x38344258) │ │ ├───Unknown (0x38345241) │ │ ├───Unknown (0x38344241) │ │ ├───XBGR8888 (0x34324258) │ │ ├───ABGR8888 (0x34324241) │ │ ├───RGB565 (0x36314752) │ │ ├───NV12 (0x3231564e) │ │ ├───XRGB16161616F (0x48345258) │ │ ├───ARGB16161616F (0x48345241) │ │ ├───XBGR16161616F (0x48344258) │ │ └───ABGR16161616F (0x48344241) │ └───Properties │ ├───"type" (immutable): enum {Overlay, Primary, Cursor} = Primary │ ├───"FB_ID" (atomic): object framebuffer = 0 │ ├───"IN_FENCE_FD" (atomic): srange [-1, INT32_MAX] = -1 │ ├───"CRTC_ID" (atomic): object CRTC = 0 │ ├───"CRTC_X" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_Y" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_W" (atomic): range [0, INT32_MAX] = 0 │ ├───"CRTC_H" (atomic): range [0, INT32_MAX] = 0 │ ├───"SRC_X" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_Y" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_W" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_H" (atomic): range [0, UINT32_MAX] = 0 │ ├───"IN_FORMATS" (immutable): blob = 46 │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008533b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008563b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008537b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008567b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008401b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ ├───RGB565 (0x36314752) │ │ │ ├───NV12 (0x3231564e) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008401903) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ ├───RGB565 (0x36314752) │ │ │ ├───NV12 (0x3231564e) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ ├───AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) (0x200000000000a01) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ ├───AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) (0x200000000000901) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ ├───RGB565 (0x36314752) │ │ │ ├───NV12 (0x3231564e) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ └───DRM_FORMAT_MOD_LINEAR (0x0) │ │ ├───XRGB8888 (0x34325258) │ │ ├───ARGB8888 (0x34325241) │ │ ├───RGBA8888 (0x34324152) │ │ ├───XRGB2101010 (0x30335258) │ │ ├───XBGR2101010 (0x30334258) │ │ ├───ARGB2101010 (0x30335241) │ │ ├───ABGR2101010 (0x30334241) │ │ ├───Unknown (0x38345258) │ │ ├───Unknown (0x38344258) │ │ ├───Unknown (0x38345241) │ │ ├───Unknown (0x38344241) │ │ ├───XBGR8888 (0x34324258) │ │ ├───ABGR8888 (0x34324241) │ │ ├───RGB565 (0x36314752) │ │ ├───NV12 (0x3231564e) │ │ ├───XRGB16161616F (0x48345258) │ │ ├───ARGB16161616F (0x48345241) │ │ ├───XBGR16161616F (0x48344258) │ │ └───ABGR16161616F (0x48344241) │ ├───"COLOR_ENCODING": enum {ITU-R BT.601 YCbCr, ITU-R BT.709 YCbCr, ITU-R BT.2020 YCbCr} = ITU-R BT.601 YCbCr │ ├───"COLOR_RANGE": enum {YCbCr limited range, YCbCr full range} = YCbCr limited range │ └───"rotation": bitmask {rotate-0, rotate-90, rotate-180, rotate-270} = (rotate-0) ├───Plane 2 │ ├───Object ID: 50 │ ├───CRTCs: {1} │ ├───FB ID: 0 │ ├───Formats: │ │ ├───XRGB8888 (0x34325258) │ │ ├───ARGB8888 (0x34325241) │ │ ├───RGBA8888 (0x34324152) │ │ ├───XRGB2101010 (0x30335258) │ │ ├───XBGR2101010 (0x30334258) │ │ ├───ARGB2101010 (0x30335241) │ │ ├───ABGR2101010 (0x30334241) │ │ ├───Unknown (0x38345258) │ │ ├───Unknown (0x38344258) │ │ ├───Unknown (0x38345241) │ │ ├───Unknown (0x38344241) │ │ ├───XBGR8888 (0x34324258) │ │ ├───ABGR8888 (0x34324241) │ │ ├───RGB565 (0x36314752) │ │ ├───NV12 (0x3231564e) │ │ ├───XRGB16161616F (0x48345258) │ │ ├───ARGB16161616F (0x48345241) │ │ ├───XBGR16161616F (0x48344258) │ │ └───ABGR16161616F (0x48344241) │ └───Properties │ ├───"type" (immutable): enum {Overlay, Primary, Cursor} = Primary │ ├───"FB_ID" (atomic): object framebuffer = 0 │ ├───"IN_FENCE_FD" (atomic): srange [-1, INT32_MAX] = -1 │ ├───"CRTC_ID" (atomic): object CRTC = 0 │ ├───"CRTC_X" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_Y" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_W" (atomic): range [0, INT32_MAX] = 0 │ ├───"CRTC_H" (atomic): range [0, INT32_MAX] = 0 │ ├───"SRC_X" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_Y" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_W" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_H" (atomic): range [0, UINT32_MAX] = 0 │ ├───"IN_FORMATS" (immutable): blob = 51 │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008533b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008563b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008537b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008567b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008401b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ ├───RGB565 (0x36314752) │ │ │ ├───NV12 (0x3231564e) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008401903) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ ├───RGB565 (0x36314752) │ │ │ ├───NV12 (0x3231564e) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ ├───AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) (0x200000000000a01) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ ├───AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) (0x200000000000901) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ ├───RGB565 (0x36314752) │ │ │ ├───NV12 (0x3231564e) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ └───DRM_FORMAT_MOD_LINEAR (0x0) │ │ ├───XRGB8888 (0x34325258) │ │ ├───ARGB8888 (0x34325241) │ │ ├───RGBA8888 (0x34324152) │ │ ├───XRGB2101010 (0x30335258) │ │ ├───XBGR2101010 (0x30334258) │ │ ├───ARGB2101010 (0x30335241) │ │ ├───ABGR2101010 (0x30334241) │ │ ├───Unknown (0x38345258) │ │ ├───Unknown (0x38344258) │ │ ├───Unknown (0x38345241) │ │ ├───Unknown (0x38344241) │ │ ├───XBGR8888 (0x34324258) │ │ ├───ABGR8888 (0x34324241) │ │ ├───RGB565 (0x36314752) │ │ ├───NV12 (0x3231564e) │ │ ├───XRGB16161616F (0x48345258) │ │ ├───ARGB16161616F (0x48345241) │ │ ├───XBGR16161616F (0x48344258) │ │ └───ABGR16161616F (0x48344241) │ ├───"COLOR_ENCODING": enum {ITU-R BT.601 YCbCr, ITU-R BT.709 YCbCr, ITU-R BT.2020 YCbCr} = ITU-R BT.601 YCbCr │ ├───"COLOR_RANGE": enum {YCbCr limited range, YCbCr full range} = YCbCr limited range │ └───"rotation": bitmask {rotate-0, rotate-90, rotate-180, rotate-270} = (rotate-0) ├───Plane 3 │ ├───Object ID: 55 │ ├───CRTCs: {0} │ ├───FB ID: 99 │ │ ├───Object ID: 99 │ │ ├───Size: 800x1280 │ │ ├───Format: ARGB8888 (0x34325241) │ │ ├───Modifier: DRM_FORMAT_MOD_LINEAR (0x0) │ │ └───Planes: │ │ └───Plane 0: offset = 0, pitch = 3328 │ ├───Formats: │ │ ├───XRGB8888 (0x34325258) │ │ ├───ARGB8888 (0x34325241) │ │ ├───RGBA8888 (0x34324152) │ │ ├───XRGB2101010 (0x30335258) │ │ ├───XBGR2101010 (0x30334258) │ │ ├───ARGB2101010 (0x30335241) │ │ ├───ABGR2101010 (0x30334241) │ │ ├───Unknown (0x38345258) │ │ ├───Unknown (0x38344258) │ │ ├───Unknown (0x38345241) │ │ ├───Unknown (0x38344241) │ │ ├───XBGR8888 (0x34324258) │ │ ├───ABGR8888 (0x34324241) │ │ ├───RGB565 (0x36314752) │ │ ├───NV12 (0x3231564e) │ │ ├───XRGB16161616F (0x48345258) │ │ ├───ARGB16161616F (0x48345241) │ │ ├───XBGR16161616F (0x48344258) │ │ └───ABGR16161616F (0x48344241) │ └───Properties │ ├───"type" (immutable): enum {Overlay, Primary, Cursor} = Primary │ ├───"FB_ID" (atomic): object framebuffer = 99 │ │ ├───Object ID: 99 │ │ ├───Size: 800x1280 │ │ ├───Format: ARGB8888 (0x34325241) │ │ ├───Modifier: DRM_FORMAT_MOD_LINEAR (0x0) │ │ └───Planes: │ │ └───Plane 0: offset = 0, pitch = 3328 │ ├───"IN_FENCE_FD" (atomic): srange [-1, INT32_MAX] = -1 │ ├───"CRTC_ID" (atomic): object CRTC = 68 │ ├───"CRTC_X" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_Y" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_W" (atomic): range [0, INT32_MAX] = 800 │ ├───"CRTC_H" (atomic): range [0, INT32_MAX] = 1280 │ ├───"SRC_X" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_Y" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_W" (atomic): range [0, UINT32_MAX] = 800 │ ├───"SRC_H" (atomic): range [0, UINT32_MAX] = 1280 │ ├───"IN_FORMATS" (immutable): blob = 56 │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008533b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008563b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008537b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008567b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008401b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ ├───RGB565 (0x36314752) │ │ │ ├───NV12 (0x3231564e) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008401903) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ ├───RGB565 (0x36314752) │ │ │ ├───NV12 (0x3231564e) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ ├───AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) (0x200000000000a01) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ ├───AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) (0x200000000000901) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XRGB2101010 (0x30335258) │ │ │ ├───XBGR2101010 (0x30334258) │ │ │ ├───ARGB2101010 (0x30335241) │ │ │ ├───ABGR2101010 (0x30334241) │ │ │ ├───Unknown (0x38345258) │ │ │ ├───Unknown (0x38344258) │ │ │ ├───Unknown (0x38345241) │ │ │ ├───Unknown (0x38344241) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ ├───RGB565 (0x36314752) │ │ │ ├───NV12 (0x3231564e) │ │ │ ├───XRGB16161616F (0x48345258) │ │ │ ├───ARGB16161616F (0x48345241) │ │ │ ├───XBGR16161616F (0x48344258) │ │ │ └───ABGR16161616F (0x48344241) │ │ └───DRM_FORMAT_MOD_LINEAR (0x0) │ │ ├───XRGB8888 (0x34325258) │ │ ├───ARGB8888 (0x34325241) │ │ ├───RGBA8888 (0x34324152) │ │ ├───XRGB2101010 (0x30335258) │ │ ├───XBGR2101010 (0x30334258) │ │ ├───ARGB2101010 (0x30335241) │ │ ├───ABGR2101010 (0x30334241) │ │ ├───Unknown (0x38345258) │ │ ├───Unknown (0x38344258) │ │ ├───Unknown (0x38345241) │ │ ├───Unknown (0x38344241) │ │ ├───XBGR8888 (0x34324258) │ │ ├───ABGR8888 (0x34324241) │ │ ├───RGB565 (0x36314752) │ │ ├───NV12 (0x3231564e) │ │ ├───XRGB16161616F (0x48345258) │ │ ├───ARGB16161616F (0x48345241) │ │ ├───XBGR16161616F (0x48344258) │ │ └───ABGR16161616F (0x48344241) │ ├───"COLOR_ENCODING": enum {ITU-R BT.601 YCbCr, ITU-R BT.709 YCbCr, ITU-R BT.2020 YCbCr} = ITU-R BT.601 YCbCr │ ├───"COLOR_RANGE": enum {YCbCr limited range, YCbCr full range} = YCbCr limited range │ └───"rotation": bitmask {rotate-0, rotate-90, rotate-180, rotate-270} = (rotate-0) ├───Plane 4 │ ├───Object ID: 60 │ ├───CRTCs: {0, 1, 2, 3, 4, 5, 6, 7} │ ├───FB ID: 100 │ │ ├───Object ID: 100 │ │ ├───Size: 256x256 │ │ ├───Format: ARGB8888 (0x34325241) │ │ ├───Modifier: DRM_FORMAT_MOD_LINEAR (0x0) │ │ └───Planes: │ │ └───Plane 0: offset = 0, pitch = 1024 │ ├───Formats: │ │ ├───XRGB8888 (0x34325258) │ │ ├───ARGB8888 (0x34325241) │ │ ├───RGBA8888 (0x34324152) │ │ ├───XBGR8888 (0x34324258) │ │ ├───ABGR8888 (0x34324241) │ │ └───RGB565 (0x36314752) │ └───Properties │ ├───"type" (immutable): enum {Overlay, Primary, Cursor} = Overlay │ ├───"FB_ID" (atomic): object framebuffer = 100 │ │ ├───Object ID: 100 │ │ ├───Size: 256x256 │ │ ├───Format: ARGB8888 (0x34325241) │ │ ├───Modifier: DRM_FORMAT_MOD_LINEAR (0x0) │ │ └───Planes: │ │ └───Plane 0: offset = 0, pitch = 1024 │ ├───"IN_FENCE_FD" (atomic): srange [-1, INT32_MAX] = -1 │ ├───"CRTC_ID" (atomic): object CRTC = 68 │ ├───"CRTC_X" (atomic): srange [INT32_MIN, INT32_MAX] = 100 │ ├───"CRTC_Y" (atomic): srange [INT32_MIN, INT32_MAX] = 200 │ ├───"CRTC_W" (atomic): range [0, INT32_MAX] = 256 │ ├───"CRTC_H" (atomic): range [0, INT32_MAX] = 256 │ ├───"SRC_X" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_Y" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_W" (atomic): range [0, UINT32_MAX] = 256 │ ├───"SRC_H" (atomic): range [0, UINT32_MAX] = 256 │ ├───"IN_FORMATS" (immutable): blob = 61 │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008533b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008563b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008537b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008567b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ └───ABGR8888 (0x34324241) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008401b03) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ └───RGB565 (0x36314752) │ │ ├───AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) (0x200000008401903) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ └───RGB565 (0x36314752) │ │ ├───AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) (0x200000000000a01) │ │ ├───AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) (0x200000000000901) │ │ │ ├───XRGB8888 (0x34325258) │ │ │ ├───ARGB8888 (0x34325241) │ │ │ ├───RGBA8888 (0x34324152) │ │ │ ├───XBGR8888 (0x34324258) │ │ │ ├───ABGR8888 (0x34324241) │ │ │ └───RGB565 (0x36314752) │ │ └───DRM_FORMAT_MOD_LINEAR (0x0) │ │ ├───XRGB8888 (0x34325258) │ │ ├───ARGB8888 (0x34325241) │ │ ├───RGBA8888 (0x34324152) │ │ ├───XBGR8888 (0x34324258) │ │ ├───ABGR8888 (0x34324241) │ │ └───RGB565 (0x36314752) │ ├───"alpha": range [0, UINT16_MAX] = 65535 │ ├───"pixel blend mode": enum {None, Pre-multiplied} = Pre-multiplied │ └───"rotation": bitmask {rotate-0, rotate-90, rotate-180, rotate-270} = (rotate-0) ├───Plane 5 │ ├───Object ID: 65 │ ├───CRTCs: {0} │ ├───FB ID: 0 │ ├───Formats: │ │ └───ARGB8888 (0x34325241) │ └───Properties │ ├───"type" (immutable): enum {Overlay, Primary, Cursor} = Cursor │ ├───"FB_ID" (atomic): object framebuffer = 0 │ ├───"IN_FENCE_FD" (atomic): srange [-1, INT32_MAX] = -1 │ ├───"CRTC_ID" (atomic): object CRTC = 0 │ ├───"CRTC_X" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_Y" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_W" (atomic): range [0, INT32_MAX] = 0 │ ├───"CRTC_H" (atomic): range [0, INT32_MAX] = 0 │ ├───"SRC_X" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_Y" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_W" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_H" (atomic): range [0, UINT32_MAX] = 0 │ ├───"IN_FORMATS" (immutable): blob = 66 │ │ └───DRM_FORMAT_MOD_LINEAR (0x0) │ │ └───ARGB8888 (0x34325241) │ └───"rotation": bitmask {rotate-0, rotate-90, rotate-180, rotate-270} = (rotate-0) ├───Plane 6 │ ├───Object ID: 69 │ ├───CRTCs: {1} │ ├───FB ID: 0 │ ├───Formats: │ │ └───ARGB8888 (0x34325241) │ └───Properties │ ├───"type" (immutable): enum {Overlay, Primary, Cursor} = Cursor │ ├───"FB_ID" (atomic): object framebuffer = 0 │ ├───"IN_FENCE_FD" (atomic): srange [-1, INT32_MAX] = -1 │ ├───"CRTC_ID" (atomic): object CRTC = 0 │ ├───"CRTC_X" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_Y" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_W" (atomic): range [0, INT32_MAX] = 0 │ ├───"CRTC_H" (atomic): range [0, INT32_MAX] = 0 │ ├───"SRC_X" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_Y" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_W" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_H" (atomic): range [0, UINT32_MAX] = 0 │ ├───"IN_FORMATS" (immutable): blob = 70 │ │ └───DRM_FORMAT_MOD_LINEAR (0x0) │ │ └───ARGB8888 (0x34325241) │ └───"rotation": bitmask {rotate-0, rotate-90, rotate-180, rotate-270} = (rotate-0) ├───Plane 7 │ ├───Object ID: 73 │ ├───CRTCs: {2} │ ├───FB ID: 0 │ ├───Formats: │ │ └───ARGB8888 (0x34325241) │ └───Properties │ ├───"type" (immutable): enum {Overlay, Primary, Cursor} = Cursor │ ├───"FB_ID" (atomic): object framebuffer = 0 │ ├───"IN_FENCE_FD" (atomic): srange [-1, INT32_MAX] = -1 │ ├───"CRTC_ID" (atomic): object CRTC = 0 │ ├───"CRTC_X" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_Y" (atomic): srange [INT32_MIN, INT32_MAX] = 0 │ ├───"CRTC_W" (atomic): range [0, INT32_MAX] = 0 │ ├───"CRTC_H" (atomic): range [0, INT32_MAX] = 0 │ ├───"SRC_X" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_Y" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_W" (atomic): range [0, UINT32_MAX] = 0 │ ├───"SRC_H" (atomic): range [0, UINT32_MAX] = 0 │ ├───"IN_FORMATS" (immutable): blob = 74 │ │ └───DRM_FORMAT_MOD_LINEAR (0x0) │ │ └───ARGB8888 (0x34325241) │ └───"rotation": bitmask {rotate-0, rotate-90, rotate-180, rotate-270} = (rotate-0) └───Plane 8 ├───Object ID: 77 ├───CRTCs: {3} ├───FB ID: 0 ├───Formats: │ └───ARGB8888 (0x34325241) └───Properties ├───"type" (immutable): enum {Overlay, Primary, Cursor} = Cursor ├───"FB_ID" (atomic): object framebuffer = 0 ├───"IN_FENCE_FD" (atomic): srange [-1, INT32_MAX] = -1 ├───"CRTC_ID" (atomic): object CRTC = 0 ├───"CRTC_X" (atomic): srange [INT32_MIN, INT32_MAX] = 0 ├───"CRTC_Y" (atomic): srange [INT32_MIN, INT32_MAX] = 0 ├───"CRTC_W" (atomic): range [0, INT32_MAX] = 0 ├───"CRTC_H" (atomic): range [0, INT32_MAX] = 0 ├───"SRC_X" (atomic): range [0, UINT32_MAX] = 0 ├───"SRC_Y" (atomic): range [0, UINT32_MAX] = 0 ├───"SRC_W" (atomic): range [0, UINT32_MAX] = 0 ├───"SRC_H" (atomic): range [0, UINT32_MAX] = 0 ├───"IN_FORMATS" (immutable): blob = 78 │ └───DRM_FORMAT_MOD_LINEAR (0x0) │ └───ARGB8888 (0x34325241) └───"rotation": bitmask {rotate-0, rotate-90, rotate-180, rotate-270} = (rotate-0)Some of the
kms_plane_alpha_blendtests are failing:(kms_plane_alpha_blend:46452) igt_debugfs-DEBUG: CRC mismatch at index 0: 0xeaf2 != 0x9f78 (kms_plane_alpha_blend:46452) igt_debugfs-CRITICAL: Test assertion failure function igt_assert_crc_equal, file ../lib/igt_debugfs.c:453: (kms_plane_alpha_blend:46452) igt_debugfs-CRITICAL: Failed assertion: !mismatch || igt_skip_crc_compare (kms_plane_alpha_blend:46452) igt_core-INFO: Stack trace: (kms_plane_alpha_blend:46452) igt_core-INFO: #0 ../lib/igt_core.c:1745 __igt_fail_assert() (kms_plane_alpha_blend:46452) igt_core-INFO: #1 ../lib/igt_debugfs.c:454 igt_assert_crc_equal() (kms_plane_alpha_blend:46452) igt_core-INFO: #2 ../tests/kms_plane_alpha_blend.c:398 alpha_7efc() (kms_plane_alpha_blend:46452) igt_core-INFO: #3 ../tests/kms_plane_alpha_blend.c:505 run_test_on_pipe_planes() (kms_plane_alpha_blend:46452) igt_core-INFO: #4 ../tests/kms_plane_alpha_blend.c:540 run_subtests() (kms_plane_alpha_blend:46452) igt_core-INFO: #5 ../tests/kms_plane_alpha_blend.c:585 __igt_unique____real_main572() (kms_plane_alpha_blend:46452) igt_core-INFO: #6 ../tests/kms_plane_alpha_blend.c:572 main() (kms_plane_alpha_blend:46452) igt_core-INFO: #7 [__libc_start_main+0xd5] (kms_plane_alpha_blend:46452) igt_core-INFO: #8 [_start+0x2e] **** END **** Subtest pipe-A-alpha-7efc: FAIL (0.778s)(There's also coverage tests failing, but these should be turned into skips.)
Driver doesn't support coverage mode so those skips are expected. Do the tests look visually correct when you them with
--interactive-debug=alland advance frame by frame?Driver exposes two hardware blending modes that match the definitions in DRM:
“None”: Blend formula that ignores the pixel alpha:
out.rgb = plane_alpha * fg.rgb + (1 - plane_alpha) * bg.rgb“Pre-multiplied”: Blend formula that assumes the pixel color values have been already pre-multiplied with the alpha channel values:
out.rgb = plane_alpha * fg.rgb + (1 - (plane_alpha * fg.alpha)) * bg.rgbMPCC_ALPHA_MULTIPLIED_MODE controls whether alpha is multiplied and MPCC_ALPHA_BLND_MODE can run in three modes:
0 - per pixel alpha blending only 1 - per pixel alpha blending with gain 2 - plane alpha onlySo you should see MPCC_ALPHA_MULTIPLIED_MODE=1, MPCC_ALPHA_BLND_MODE=0, and MPCC_MODE=MPCC_BLEND_MODE_TOP_BOT_BLENDING to be able to blend with the bottom plane instead of the pipe's background color.
Edited by Nicholas KazlauskasThanks for all of the info! These are the values I see when I run the reproducer in the issue description:
[ 51.526229] mpc1_insert_plane(mpcc_id=0, insert_above_mpcc=0000000000000000) [ 51.526245] mpc2_update_blending(mpcc_id=0, MPCC_ALPHA_BLND_MODE=0, MPCC_ALPHA_MULTIPLIED_MODE=1, MPCC_BLND_ACTIVE_OVERLAP_ONLY=0, MPCC_GLOBAL_ALPHA=255, MPCC_GLOBAL_GAIN=255, MPCC_BOT_GAIN_MODE=0) [ 51.526382] mpc1_insert_plane(mpcc_id=2, insert_above_mpcc=0000000000000000) [ 51.526390] mpc2_update_blending(mpcc_id=2, MPCC_ALPHA_BLND_MODE=0, MPCC_ALPHA_MULTIPLIED_MODE=1, MPCC_BLND_ACTIVE_OVERLAP_ONLY=0, MPCC_GLOBAL_ALPHA=255, MPCC_GLOBAL_GAIN=255, MPCC_BOT_GAIN_MODE=0) [ 51.526492] mpc1_insert_plane(mpcc_id=3, insert_above_mpcc=0000000000000000) [ 51.526499] mpc2_update_blending(mpcc_id=3, MPCC_ALPHA_BLND_MODE=2, MPCC_ALPHA_MULTIPLIED_MODE=0, MPCC_BLND_ACTIVE_OVERLAP_ONLY=0, MPCC_GLOBAL_ALPHA=255, MPCC_GLOBAL_GAIN=255, MPCC_BOT_GAIN_MODE=0) [ 51.526628] mpc1_insert_plane(mpcc_id=1, insert_above_mpcc=0000000000000000) [ 51.526636] mpc2_update_blending(mpcc_id=1, MPCC_ALPHA_BLND_MODE=2, MPCC_ALPHA_MULTIPLIED_MODE=0, MPCC_BLND_ACTIVE_OVERLAP_ONLY=0, MPCC_GLOBAL_ALPHA=255, MPCC_GLOBAL_GAIN=255, MPCC_BOT_GAIN_MODE=0)Patch used to get these values:
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index 11019c2c62cc..49fb6034ae27 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -76,6 +76,7 @@ static void mpc1_update_blending( struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); + printk("mpc1_update_blending(mpcc_id=%d, MPCC_ALPHA_BLND_MODE=%d, MPCC_ALPHA_MULTIPLIED_MODE=%d, MPCC_BLND_ACTIVE_OVERLAP_ONLY=%d, MPCC_GLOBAL_ALPHA=%d, MPCC_GLOBAL_GAIN=%d)\n", mpcc_id, blnd_cfg->alpha_mode, blnd_cfg->pre_multiplied_alpha, blnd_cfg->overlap_only, blnd_cfg->global_alpha, blnd_cfg->global_gain); REG_UPDATE_5(MPCC_CONTROL[mpcc_id], MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha, @@ -212,6 +213,7 @@ struct mpcc *mpc1_insert_plane( new_mpcc->dpp_id = dpp_id; /* program mux and MPCC_MODE */ + printk("mpc1_insert_plane(mpcc_id=%d, insert_above_mpcc=%p)\n", mpcc_id, insert_above_mpcc); if (insert_above_mpcc) { new_mpcc->mpcc_bot = insert_above_mpcc; REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c index 947eb0df3f12..a5c56f86b0ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c @@ -54,6 +54,7 @@ void mpc2_update_blending( struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); + printk("mpc2_update_blending(mpcc_id=%d, MPCC_ALPHA_BLND_MODE=%d, MPCC_ALPHA_MULTIPLIED_MODE=%d, MPCC_BLND_ACTIVE_OVERLAP_ONLY=%d, MPCC_GLOBAL_ALPHA=%d, MPCC_GLOBAL_GAIN=%d, MPCC_BOT_GAIN_MODE=%d)\n", mpcc_id, blnd_cfg->alpha_mode, blnd_cfg->pre_multiplied_alpha, blnd_cfg->overlap_only, blnd_cfg->global_alpha, blnd_cfg->global_gain, blnd_cfg->bottom_gain_mode); REG_UPDATE_7(MPCC_CONTROL[mpcc_id], MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha,What strikes me is that
insert_planeis never called with a non-NULLinsert_above_mpcc, so there will always beMPCC_MODE=MPCC_BLEND_MODE_TOP_LAYER_ONLYfor all planes.The only
insert_planecall-site is indcnXX_hw_sequencer.c, but theinsert_above_mpccarg is hardcoded to NULL. Should we add a special case for the overlay plane there, and somehow get thestruct mpcc *from somewhere else?Edited by Simon SerI don't know if we had a usecase to use per pixel alpha before on an overlay, most overlay usage would have been global alpha or a transparent cutout in the last few years.
One clarification I want to make to the above blending formulas is how the hardware treats alpha, it's actually has some quirks.
For
MPCC_ALPHA_MULTIPLIED_MODE:0 - Per pixel alpha using DPP alpha value 1 - Per pixel alpha using DPP alpha value multiplied by alpha gain 2 - Global alpha valueThe
fg.alphacan be treated as DPP alpha but the alpha channel needs to be enabled for the FB. We should be doing this for the A* variants automatically.I think this means that in order to achieve a
plane_alpha * fg.alphavalue you can't actually use global alpha, you have to put global alpha into global gain instead.For your usecase plane_alpha is 0xffff anyway though, so you can treat the multiplier as 1.0 (or 0x1f000 in the FP format in the register) and ignore this detail.
Edited by Nicholas KazlauskasHi @emersion ,
I was trying to reproduce this issue today. All the tool installations were successful, however when running the tentative command, I met this error:
sudo ./tentative kms.config drmModeAtomicCommit failed: Permission denied
I am wondering is there any thing that I am missing here? Any help would be really appreciated.
Thanks a lot @daenzer for your reply and help, yes exactly, after switching from GUI mode to text mode, I don't see "drmModeAtomicCommit failed: Permission denied" anymore.
However, I met another issue here: when running "sudo ./tentative kms.config", I got "drmModeAtomicCommit failed: Invalid argument". May I get @daenzer or @emersion 's hint on what should I do to avoid this failure? I really appreciate your help on this.
Below is my kms.config: (I've checked and confirmed this is the correct CRTC_ID on my system)
plane 55 { CRTC_ID crtc 78 CRTC_X value 10 CRTC_Y value 20 FB_ID fb { size 128x128 fill_color "#FF0000" } }kms.configEdited by Zhan@zhan, thank you for looking at this issue.
I can confirm that I can still reproduce the issue on amd-staging-drm-next 6b9fcbfc0326 ("drm/amd/display: Force link_rate as LINK_RATE_RBR2 for 2018 15" Apple Retina panels").
There are many reasons why amdgpu might reject the atomic commit. You can figure that out by looking at kernel logs. More info here: https://gitlab.freedesktop.org/wlroots/wlroots/-/wikis/DRM-Debugging
mentioned in issue #1734 (closed)
Hi,
I got the expected behavior by doing the change below and I tried to figure out what is happening here:
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -2366,11 +2366,10 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) blnd_cfg.top_gain = 0x1f000; blnd_cfg.bottom_inside_gain = 0x1f000; blnd_cfg.bottom_outside_gain = 0x1f000; - blnd_cfg.pre_multiplied_alpha = per_pixel_alpha; + blnd_cfg.pre_multiplied_alpha = false; if (pipe_ctx->plane_state->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) blnd_cfg.pre_multiplied_alpha = false;
Pre-multiplied alpha is the DRM default pixel blend mode, and the AMD display driver is assuming this to configure
MPCC_ALPHA_MULTIPLIED_MODE. Also, considering the pre-multiplied formula“Pre-multiplied”: Blend formula that assumes the pixel color values have been already pre-multiplied with the alpha channel values:
out.rgb = plane_alpha * fg.rgb + (1 - (plane_alpha * fg.alpha)) * bg.rgbConsidering the composition on top of a black bg, if
plane_alpha = 1.0andbg.rgb = 0(black), I see:plane_alpha * fg.rgb => 1*fg.rgb-
(1 - (plane_alpha * fg.alpha)) * bg.rgb => (1 - (plane_alpha * fg.alpha)) * 0 => 0thanout.rgb = fg.rgbthat means it only depends on fg.rgb value, right?
But if we are seeing a solid red in the gradient portion (as previously reported), it means fg.rgb is always
#FF0000and not a pre-multiplied alpha value for each channel. For example, if alpha is 80, the pre-multiplied rgb for red would be#800000, right?So I started to suspect that the pixel color values in the file filling the overlay plane weren't pre-multiplied. And this suspicion matches the reason I get the expected results when I set
blnd_cfg.pre_multiplied_alpha = false.I also checked the drm-convert script and briefly searched for configuring magick to use pre-multiplied alpha. I found something about setting
-alphain args to get a pre-multiplied result.. but, I'm not sure how magick works tbh. @emersion, Do you know if the file is using or not pre-multiplied color values?If pixel color values are not the issue, I would be grateful if someone has any thoughts to share that could explain why this change led to the expected result.
In addition, I wonder if using a combination of
MPCC_ALPHA_MULTIPLIED_MODE = 0andMPCC_ALPHA_BLND_MODE = MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAINmay leads us to enable the coverage blend mode. Because I understand a coverage pixel blend mode is the reason I got the expected result using no pre-multiplied pixel values , and this combination seems to deliver elements for the coverage equation.Hi, I was also able to resolve this issue.
According to the DRM/KMS man page (under section Plane Composition Properties), there is a property called "pixel blend mode" that needs to be explicitly set for PNG images (the file format of the source image that gets converted to a raw buffer and used as an input for tentative app). It's basically a property that selects the alpha blending equation to be used in HW and there are 3 types as described below in the screenshot. https://dri.freedesktop.org/docs/drm/gpu/drm-kms.html#plane-composition-properties
"None" would just mean that there is no overlay plane present so we can ignore that for now. When there are overlay planes, we consider 2 more types: "Pre-multiplied" and "Coverage" (which is basically "Not Pre-multipled"). In the current driver implementation, we always assume that the overlay plane already has pixels "Pre-multiplied" with the alpha values by default, but the issue is, that's not the case for PNG images. After some web searching, it seems like when the PNG images are created, the pixels are not "Pre-multiplied" and hence we need to indicate that to the driver by specifying the pixel blend mode property in the KMS config file for the overlay plane.
I'm attaching two files here. One for the patch (0001-drm-amd-display-Fix-alpha-blending-bug-with-overlay-.patch) with the fix and the other with the KMS config file (alpha_blend) used for "tentative" application.
With the new KMS config file and the /display patch, I was able to see an image that looked the same as the expected image.
@emersion, Please give them a try and see it resolves the issue on your side.
Thanks!
-
@sungkim, your patch makes sense to me. IIUC, this change would also allow us to run
coverage modetest cases in the IGT kms_alpha_blend that are currently skipped, right?
Hi @mwen, initially, "coverage mode" wasn't part of our IGT kms_alpha_blend test case. But since it's enabled now in our driver with the patch I provided, I believe we should be able to.
mentioned in commit agd5f/linux@a6b5d5b6
mentioned in commit agd5f/linux@76818cdd
Hi @emersion , We already have the fix merged into amd-staging-drm-next and IGT tests (https://patchwork.freedesktop.org/series/104366/). Are you ok with closing this issue?
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