RX 5500 XT: PCIe link speed stuck at Gen1 2.5GT/s by default
I'm using a RX 5500 XT card on an Asus PRIME H270-PRO motherboard, Intel i5-7500 CPU, with kernel 5.10.9 under Fedora 33. I noticed that in Linux, "lspci -vv" always showed the GPU PCIe link running at 2.5GT/s link speed and never seemed to change regardless of the application being run, while in Windows, GPU-Z shows the link running at the max supported 8GT/s speed when under graphical load.
It seems like the driver thinks that 2.5GT/s is the max allowable speed, based on the pp_dpm_pcie file:
> cd /sys/devices/pci0000:00/0000:00:01.0/0000:01:00.0/0000:02:00.0/0000:03:00.0/
> cat pp_dpm_pcie
0: 2.5GT/s, x8 81Mhz *
1: 2.5GT/s, x8 619Mhz *I'm assuming that something is going wrong with the PCIe link speed detection in the driver. Using the "amdgpu.pcie_gen_cap=0x70007" kernel command line option seems to result in the driver detecting the proper 8GT/s maximum speed.
lspci -vv output from booting without overriding the speed is attached.
Activity
With "amdgpu.pcie_gen_cap=0x70007" on the command line, pp_dpm_pcie reports:
0: 2.5GT/s, x8 81Mhz 1: 8.0GT/s, x8 619Mhz *lspci with this setup is attached.
The driver calls the pci core function pcie_bandwidth_available() to get the available link speed and lanes between it and the root complex. Presumably some link in that path is limited to 2.5GT/s or there is some issue in pcie_bandwidth_available() on your board.
Edited by Alex DeucherI think that same function is used in the code that prints this output in dmesg on boot. It's saying the CPU PCIe root port is limiting the link speed:
pci 0000:01:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x8 link at 0000:00:01.0 (capable of 126.024 Gb/s with 16.0 GT/s PCIe x8 link) pci 0000:03:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x8 link at 0000:00:01.0 (capable of 252.048 Gb/s with 16.0 GT/s PCIe x16 link)But that's wrong, since that link is clearly capable of 8GT/s:
00:01.0 PCI bridge: Intel Corporation 6th-10th Gen Core Processor PCIe Controller (x16) (rev 05) (prog-if 00 [Normal decode]) ... Capabilities: [a0] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0 ExtTag- RBE+ DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 256 bytes, MaxReadReq 128 bytes DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 8GT/s, Width x16, ASPM L0s L1, Exit Latency L0s <256ns, L1 <8us ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+ LnkSta: Speed 8GT/s (ok), Width x8 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt+ ABWMgmt+It seems like pcie_bandwidth_available is just looking at the LnkSta register to determine how much bandwidth is available. After boot, it apparently shows a speed of 2.5GT/s. Maybe that's the speed the GPU's link comes up at on boot, which results in this code thinking it can't run any faster?
There's only one link in the path here, between the CPU and GPU, and both ends are capable of 8GT/s, so nothing else should be limiting throughput.
Maybe pcie_bandwidth_available should be looking at the link capability rather than link status for each link in the chain, to handle the case where a link is running below its maximum speed on boot. This usage in amdgpu may be a case that code wasn't designed for though, as amdgpu really wants to know what the maximum bandwidth could be set to, not just what it currently is.
I'm not sure why the link ends up at 2.5GT/s on boot before the driver loads though. Is that expected? There is a BIOS option for the PEG link speed, I tried Auto and Gen3 which seemed to behave the same. Maybe the GPU downclocks to 2.5 on its own before the OS even loads? Not sure how that mechanism works.
My understanding is that generally the links usually train at max speed supported by both ends. I wonder if Intel bridge port has some sort of power management feature that dynamically adjusts the link similar to what the GPU does? In general, I've always found that the link comes up at the max speed when the endpoint comes out of reset.
So after experimenting with BIOS options a bit, it appears that the PEG ASPM option affects this behavior. It appears if this is set to L0s, L1 or L0sL1, the link comes up at 2.5GT/s on boot. Oddly, even if it's set to L0s, which the card doesn't seem to support on the upstream PCIe port, it still comes up at 2.5GT/s. If it's set to Disabled or Auto, it comes up at 8GT/s.
Looking at some amdgpu code, it seems that some other chip generations have some (rather complex) code to enable ASPM support, but nv.c seems to have a note that "The ASPM function is not fully enabled and verified on Navi yet. Temporarily skip this until ASPM enabled." Maybe there's some more driver-level support required to support ASPM properly? I'm not sure if the weird link speed issue is expected behavior with it enabled in the current state?
Minor detail, there are two links in this path: 00:01.0 - 01:00.0 (root port to switch) and 02:00.0 - 03:00.0 (switch to Navi). Per LnkCap, the best we can hope for is 8GT/s x8, limited by the rate of the root port and the width of the switch upstream port.
The first lspci (no override) LnkSta shows 2.5GT/s x8 on the upstream link and 16GT/s x16 on the downstream one, which lines up with the dmesg. The "available" comes from LnkSta, i.e., the current state of the link, and the "capable" part comes from LnkCap. I think the point of those messages was to identify cases like this where we're operating slower than we could.
I don't know why the upstream link comes up at 2.5GT/s x8 instead of 8GT/s x8. The PCI core doesn't do anything to influence that. We just assume the link trains at the highest rate/width supported by both ends, which I think is what the spec envisions.
The PCI core also does nothing to limit the downstream link to 4GT/s x16 or similar for power savings. Maybe it should, I dunno? But not relevant to this problem.
I can also confirm this issue with an RX 6700 XT eGPU;
LnkStawon't go above 2.5GT/s no mapper the load:1:00.0 PCI bridge: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge DD 2018] (rev 06) (prog-if 00 [Normal decode]) Physical Slot: 5 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 IOMMU group: 17 Bus: primary=41, secondary=42, subordinate=46, sec-latency=0 I/O behind bridge: 3000-3fff [size=4K] [16-bit] Memory behind bridge: 72000000-723fffff [size=4M] [32-bit] Prefetchable memory behind bridge: 4200000000-47ffffffff [size=24G] [32-bit] Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [80] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [88] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [ac] Subsystem: Device 0000:0000 Capabilities: [c0] Express (v2) Upstream Port, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0 ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ SlotPowerLimit 0W DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr+ TransPend- LnkCap: Port #3, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <2us ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; Disabled- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s (downgraded), Width x4 TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR+ 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix- EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- FRS- AtomicOpsCap: Routing- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled, AtomicOpsCtl: EgressBlck- LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- Retimer- 2Retimers- DRS- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete- EqualizationPhase1- EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest- Retimer- 2Retimers- CrosslinkRes: unsupportedNote the
(downgraded). This on an XPS 13 Plus running Fedora 37 on Kernel6.1.13. I've tried addingamdgpu.pcie_gen_cap=0x00040000to kernel params and checked that it was set successfully in/proc/cmdline, but it still doesn't reach full speeds which leads to really significant performance issues in games such as e.g. Cyberpunk 2077.Some more posts that have referenced this issue now:
- https://gitea.quad.moe/quad/win3-resources/src/branch/master/docs/eGPU.md
- https://community.frame.work/t/guide-egpu-performance-tests-using-amd-rx-580-on-linux/26384
Screenshot to confirming this under load with
glmark2:
Edited by Felicitas PojtingerThe problem is the thunderbolt link. The thunderbolt bridge come up in 2.5GT/s mode. The GPU driver queries the upstream bridges and limits it's speed to the max current speed of the upstream bridge it's connected to. There is no reason to run the link clocks faster if you are limited by a bridge above you. If the thunderbolt bridge can change it's link speed at runtime, we probably need to rework the core PCI code to take that into account when reporting the upstream bridge link speeds.
The same problem occurred on RX 6600.
Also, there is no asterisk attached to the current state on RX 6600 (Navi23) and RX 7900 XTX (Navi31).
https://github.com/Syllo/nvtop/issues/242#issuecomment-1735075492- CPU: Ryzen 5 5600G
- GPU: RX 6600 (Running at Gen3x8)
- Kernel version: 6.5.2
$ cat /sys/class/drm/card0/device/pp_dpm_pcie 0: 2.5GT/s, 81Mhz 1: 2.5GT/s, 619Mhzgpu_metrics
GPU Metrics V1_3( gpu_metrics_v1_3 { common_header: metrics_table_header { structure_size: 120, format_revision: 1, content_revision: 3, }, temperature_edge: 54, temperature_hotspot: 56, temperature_mem: 52, temperature_vrgfx: 0, temperature_vrsoc: 0, temperature_vrmem: 0, average_gfx_activity: 4, average_umc_activity: 0, average_mm_activity: 0, average_socket_power: 23, energy_accumulator: 0, system_clock_counter: 841007722732, average_gfxclk_frequency: 53, average_socclk_frequency: 65535, average_uclk_frequency: 870, average_vclk0_frequency: 666, average_dclk0_frequency: 555, average_vclk1_frequency: 0, average_dclk1_frequency: 0, current_gfxclk: 700, current_socclk: 800, current_uclk: 875, current_vclk0: 666, current_dclk0: 555, current_vclk1: 0, current_dclk1: 0, throttle_status: 0, current_fan_speed: 0, pcie_link_width: 8, pcie_link_speed: 80, padding: 65535, gfx_activity_acc: 4294967295, mem_activity_acc: 4294967295, temperature_hbm: [ 65535, 65535, 65535, 65535, ], firmware_timestamp: 18446744073709551615, voltage_soc: 65535, voltage_gfx: 65535, voltage_mem: 65535, padding1: 65535, indep_throttle_status: 0, }, )pp_table
smu_11_0_7_powerplay_table { header: atom_common_table_header { structuresize: 2470, format_revision: 18, content_revision: 0, }, table_revision: 2, table_size: 802, golden_pp_id: 2500, golden_revision: 17299, format_id: 131, platform_caps: 8, thermal_controller_type: 28, small_power_limit1: 0, small_power_limit2: 0, boost_power_limit: 0, software_shutdown_temp: 118, reserve: [ 0, 0, 0, 0, 0, 0, 1, 0, ], power_saving_clock: smu_11_0_7_power_saving_clock_table { revision: 1, reserve: [ 0, 0, 0, ], count: 13, max: [ 2750, 1280, 875, 1800, 1250, 1429, 1250, 1429, 1200, 1217, 1217, 810, 1217, 0, 0, 0, ], min: [ 500, 418, 97, 500, 572, 690, 572, 690, 418, 487, 487, 300, 487, 0, 0, 0, ], }, overdrive_table: smu_11_0_7_overdrive_table { revision: 129, reserve: [ 0, 0, 0, ], feature_count: 16, setting_count: 30, cap: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ], max: [ 2900, 2900, 0, 0, 0, 2900, 950, 950, 20, 3600, 3600, 110, 110, 1, 1, 1, 1, 1, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ], min: [ 500, 500, 0, 0, 0, 500, 674, 674, 6, 25, 1000, 25, 50, 0, 0, 0, 0, 0, 25, 10, 25, 10, 25, 10, 25, 10, 25, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ], pm_setting: [ 6, 0, 6, 0, 95, 95, 95, 95, 4500, 4500, 1750, 1750, 6000, 6000, 2250, 2250, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ], }, smc_pptable: PPTable_t { Version: 6, FeaturesToRun: [ 2743074303, 276451, ], SocketPowerLimitAc: [ 100, 0, 0, 0, ], SocketPowerLimitAcTau: [ 0, 0, 0, 0, ], SocketPowerLimitDc: [ 100, 0, 0, 0, ], SocketPowerLimitDcTau: [ 0, 0, 0, 0, ], TdcLimit: [ 100, 18, ], TdcLimitTau: [ 0, 0, ], TemperatureLimit: [ 100, 110, 100, 115, 115, 115, 115, 0, 0, 0, ], FitLimit: 0, TotalPowerConfig: 1, TotalPowerPadding: [ 0, 0, 0, ], ApccPlusResidencyLimit: 10, SmnclkDpmFreq: [ 0, 0, ], SmnclkDpmVoltage: [ 0, 0, ], PaddingAPCC: 0, PerPartDroopVsetGfxDfll: [ 3000, 3400, 3800, 4200, 4800, ], PaddingPerPartDroop: 0, ThrottlerControlMask: 14348, FwDStateMask: 16383, UlvVoltageOffsetSoc: 50, UlvVoltageOffsetGfx: 100, MinVoltageUlvGfx: 0, MinVoltageUlvSoc: 3000, SocLIVmin: 3000, PaddingLIVmin: 50, GceaLinkMgrIdleThreshold: 0, paddingRlcUlvParams: [ 0, 0, 0, ], MinVoltageGfx: 3094, MinVoltageSoc: 3050, MaxVoltageGfx: 4600, MaxVoltageSoc: 4200, LoadLineResistanceGfx: 128, LoadLineResistanceSoc: 256, VDDGFX_TVmin: 55, VDDSOC_TVmin: 55, VDDGFX_Vmin_HiTemp: 3094, VDDGFX_Vmin_LoTemp: 3094, VDDSOC_Vmin_HiTemp: 3050, VDDSOC_Vmin_LoTemp: 3050, VDDGFX_TVminHystersis: 5, VDDSOC_TVminHystersis: 5, DpmDescriptor: [ DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 0, NumDiscreteLevels: 2, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1065353216, b: 0, }, SsCurve: QuadraticInt_t { a: 1040782648, b: 3185885944, c: 1059593262, }, SsFmin: 417, Padding16: 0, }, DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 0, NumDiscreteLevels: 2, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1066049470, b: 1048240456, }, SsCurve: QuadraticInt_t { a: 989485303, b: 1055723094, c: 1051416047, }, SsFmin: 418, Padding16: 0, }, DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 1, NumDiscreteLevels: 4, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1067072881, b: 1042871747, }, SsCurve: QuadraticInt_t { a: 991646208, b: 1057216266, c: 1049905091, }, SsFmin: 97, Padding16: 0, }, DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 0, NumDiscreteLevels: 2, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1065353216, b: 0, }, SsCurve: QuadraticInt_t { a: 987080121, b: 1054515134, c: 1048743772, }, SsFmin: 500, Padding16: 0, }, DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 0, NumDiscreteLevels: 2, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1067198710, b: 1042066440, }, SsCurve: QuadraticInt_t { a: 991903907, b: 1057316930, c: 1048730350, }, SsFmin: 572, Padding16: 0, }, DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 0, NumDiscreteLevels: 2, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1065504211, b: 1045086339, }, SsCurve: QuadraticInt_t { a: 987595517, b: 1054783570, c: 1048731021, }, SsFmin: 690, Padding16: 0, }, DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 0, NumDiscreteLevels: 2, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1067198710, b: 1042066440, }, SsCurve: QuadraticInt_t { a: 991903907, b: 1057316930, c: 1048730350, }, SsFmin: 572, Padding16: 0, }, DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 0, NumDiscreteLevels: 2, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1065504211, b: 1045086339, }, SsCurve: QuadraticInt_t { a: 987595517, b: 1054783570, c: 1048731021, }, SsFmin: 690, Padding16: 0, }, DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 0, NumDiscreteLevels: 2, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1066995705, b: 1050253722, }, SsCurve: QuadraticInt_t { a: 992677001, b: 1057635697, c: 1048732699, }, SsFmin: 418, Padding16: 0, }, DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 0, NumDiscreteLevels: 2, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1066947052, b: 1041328243, }, SsCurve: QuadraticInt_t { a: 991818007, b: 1057283375, c: 1048731021, }, SsFmin: 487, Padding16: 0, }, DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 0, NumDiscreteLevels: 2, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1066947052, b: 1041328243, }, SsCurve: QuadraticInt_t { a: 991818007, b: 1057283375, c: 1048731021, }, SsFmin: 487, Padding16: 0, }, DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 0, NumDiscreteLevels: 2, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1060622041, b: 1060773036, }, SsCurve: QuadraticInt_t { a: 0, b: 1049585988, c: 1058224577, }, SsFmin: 300, Padding16: 0, }, DpmDescriptor_t { VoltageMode: 0, SnapToDiscrete: 0, NumDiscreteLevels: 2, Padding: 0, ConversionToAvfsClk: LinearInt_t { m: 1066947052, b: 1041328243, }, SsCurve: QuadraticInt_t { a: 991818007, b: 1057283375, c: 1048731021, }, SsFmin: 487, Padding16: 0, }, ], FreqTableGfx: [ 500, 2750, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ], FreqTableVclk: [ 690, 1429, 0, 0, 0, 0, 0, 0, ], FreqTableDclk: [ 572, 1250, 0, 0, 0, 0, 0, 0, ], FreqTableSocclk: [ 418, 1280, 0, 0, 0, 0, 0, 0, ], FreqTableUclk: [ 97, 542, 676, 875, ], FreqTableDcefclk: [ 418, 1200, 0, 0, 0, 0, 0, 0, ], FreqTableDispclk: [ 487, 1217, 0, 0, 0, 0, 0, 0, ], FreqTablePixclk: [ 487, 1217, 0, 0, 0, 0, 0, 0, ], FreqTablePhyclk: [ 300, 810, 0, 0, 0, 0, 0, 0, ], FreqTableDtbclk: [ 487, 1217, 0, 0, 0, 0, 0, 0, ], FreqTableFclk: [ 500, 1800, 0, 0, 0, 0, 0, 0, ], Paddingclks: 0, PerPartDroopModelGfxDfll: [ DroopInt_t { a: 1065431230, b: 1028389654, c: 3177848987, }, DroopInt_t { a: 1065431230, b: 1028389654, c: 3177848987, }, DroopInt_t { a: 1065431230, b: 1028389654, c: 3177848987, }, DroopInt_t { a: 1063394644, b: 1038710997, c: 3183121059, }, DroopInt_t { a: 1059510047, b: 1039918957, c: 1043637459, }, ], DcModeMaxFreq: [ 2750, 1280, 875, 1800, 1250, 1429, 1250, 1429, 1200, 1217, 1217, 810, 1217, ], FreqTableUclkDiv: [ 0, 3, 3, 3, ], FclkBoostFreq: 1800, FclkParamPadding: 0, Mp0clkFreq: [ 332, 506, ], Mp0DpmVoltage: [ 2800, 3200, ], MemVddciVoltage: [ 2700, 3400, 3400, 3400, ], MemMvddVoltage: [ 5000, 5400, 5400, 5400, ], GfxclkFgfxoffEntry: 700, GfxclkFinit: 800, GfxclkFidle: 700, GfxclkSource: 1, GfxclkPadding: 0, GfxGpoSubFeatureMask: 1, GfxGpoEnabledWorkPolicyMask: 2, GfxGpoDisabledWorkPolicyMask: 93, GfxGpoPadding: [ 0, ], GfxGpoVotingAllow: 1, GfxGpoPadding32: [ 0, 0, 0, 0, ], GfxDcsFopt: 0, GfxDcsFclkFopt: 0, GfxDcsUclkFopt: 0, DcsGfxOffVoltage: 0, DcsMinGfxOffTime: 0, DcsMaxGfxOffTime: 0, DcsMinCreditAccum: 0, DcsExitHysteresis: 0, DcsTimeout: 0, DcsParamPadding: [ 0, 0, 0, 0, 0, ], FlopsPerByteTable: [ 4332, 4228, 4124, 4021, 3917, 3813, 3710, 3606, 3502, 3399, 3295, 3191, 2906, 2621, 2336, 2051, ], LowestUclkReservedForUlv: 0, PaddingMem: [ 0, 0, 0, ], UclkDpmPstates: [ 3, 2, 1, 0, ], UclkDpmSrcFreqRange: UclkDpmChangeRange_t { Fmin: 0, Fmax: 0, }, UclkDpmTargFreqRange: UclkDpmChangeRange_t { Fmin: 0, Fmax: 0, }, UclkDpmMidstepFreq: 0, UclkMidstepPadding: 0, PcieGenSpeed: [ 0, 3, ], PcieLaneCount: [ 1, 4, ], LclkFreq: [ 81, 619, ], FanStopTemp: 50, FanStartTemp: 60, FanGain: [ 0, 400, 400, 0, 0, 0, 0, 0, 0, 0, ], FanPwmMin: 15, FanAcousticLimitRpm: 1800, FanThrottlingRpm: 3600, FanMaximumRpm: 3600, MGpuFanBoostLimitRpm: 0, FanTargetTemperature: 86, FanTargetGfxclk: 500, FanPadding16: 0, FanTempInputSelect: 1, FanPadding: 0, FanZeroRpmEnable: 1, FanTachEdgePerRev: 2, FuzzyFan_ErrorSetDelta: 0, FuzzyFan_ErrorRateSetDelta: 0, FuzzyFan_PwmSetDelta: 0, FuzzyFan_Reserved: 0, OverrideAvfsGb: [ 0, 0, ], dBtcGbGfxDfllModelSelect: 3, Padding8_Avfs: 0, qAvfsGb: [ QuadraticInt_t { a: 0, b: 0, c: 0, }, QuadraticInt_t { a: 0, b: 0, c: 0, }, ], dBtcGbGfxPll: DroopInt_t { a: 1032188015, b: 3178342908, c: 1035799814, }, dBtcGbGfxDfll: DroopInt_t { a: 0, b: 0, c: 0, }, dBtcGbSoc: DroopInt_t { a: 1041968461, b: 1025114741, c: 3162985715, }, qAgingGb: [ LinearInt_t { m: 0, b: 0, }, LinearInt_t { m: 0, b: 0, }, ], PiecewiseLinearDroopIntGfxDfll: PiecewiseLinearDroopInt_t { Fset: [ 0, 0, 0, 0, 0, ], Vdroop: [ 0, 0, 0, 0, 0, ], }, qStaticVoltageOffset: [ QuadraticInt_t { a: 0, b: 0, c: 0, }, QuadraticInt_t { a: 0, b: 0, c: 0, }, ], DcTol: [ 225, 225, ], DcBtcEnabled: [ 1, 1, ], Padding8_GfxBtc: [ 0, 0, ], DcBtcMin: [ 0, 0, ], DcBtcMax: [ 225, 225, ], DcBtcGb: [ 25, 25, ], XgmiDpmPstates: [ 0, 0, ], XgmiDpmSpare: [ 0, 0, ], DebugOverrides: 0, ReservedEquation0: QuadraticInt_t { a: 0, b: 0, c: 0, }, ReservedEquation1: QuadraticInt_t { a: 0, b: 0, c: 0, }, ReservedEquation2: QuadraticInt_t { a: 0, b: 0, c: 0, }, ReservedEquation3: QuadraticInt_t { a: 0, b: 0, c: 0, }, CustomerVariant: 0, VcBtcEnabled: 1, VcBtcVminT0: 2900, VcBtcFixedVminAgingOffset: 52, VcBtcVmin2PsmDegrationGb: 0, VcBtcPsmA: 1078293902, VcBtcPsmB: 1047032496, VcBtcVminA: 1099196006, VcBtcVminB: 1053545411, LedGpio: 0, GfxPowerStagesGpio: 0, SkuReserved: [ 196611000, 209718400, 14745800, 225, 0, 0, 0, 0, ], GamingClk: [ 1845, 2044, 2491, 1845, 2044, 2491, ], I2cControllers: [ I2cControllerConfig_t { Enabled: 0, Speed: 0, SlaveAddress: 0, ControllerPort: 0, ControllerName: 0, ThermalThrotter: 0, I2cProtocol: 0, PaddingConfig: 0, }, I2cControllerConfig_t { Enabled: 0, Speed: 0, SlaveAddress: 0, ControllerPort: 0, ControllerName: 0, ThermalThrotter: 0, I2cProtocol: 26, PaddingConfig: 1, }, I2cControllerConfig_t { Enabled: 1, Speed: 245, SlaveAddress: 173, ControllerPort: 128, ControllerName: 25, ThermalThrotter: 8, I2cProtocol: 104, PaddingConfig: 1, }, I2cControllerConfig_t { Enabled: 1, Speed: 5, SlaveAddress: 72, ControllerPort: 28, ControllerName: 220, ThermalThrotter: 3, I2cProtocol: 11, PaddingConfig: 0, }, I2cControllerConfig_t { Enabled: 0, Speed: 0, SlaveAddress: 192, ControllerPort: 208, ControllerName: 224, ThermalThrotter: 240, I2cProtocol: 165, PaddingConfig: 1, }, I2cControllerConfig_t { Enabled: 1, Speed: 170, SlaveAddress: 25, ControllerPort: 0, ControllerName: 0, ThermalThrotter: 0, I2cProtocol: 116, PaddingConfig: 1, }, I2cControllerConfig_t { Enabled: 1, Speed: 5, SlaveAddress: 255, ControllerPort: 255, ControllerName: 255, ThermalThrotter: 255, I2cProtocol: 50, PaddingConfig: 1, }, I2cControllerConfig_t { Enabled: 1, Speed: 175, SlaveAddress: 0, ControllerPort: 0, ControllerName: 0, ThermalThrotter: 142, I2cProtocol: 1, PaddingConfig: 0, }, I2cControllerConfig_t { Enabled: 0, Speed: 0, SlaveAddress: 23, ControllerPort: 0, ControllerName: 0, ThermalThrotter: 0, I2cProtocol: 23, PaddingConfig: 0, }, I2cControllerConfig_t { Enabled: 0, Speed: 0, SlaveAddress: 146, ControllerPort: 87, ControllerName: 43, ThermalThrotter: 5, I2cProtocol: 0, PaddingConfig: 0, }, I2cControllerConfig_t { Enabled: 1, Speed: 0, SlaveAddress: 101, ControllerPort: 0, ControllerName: 110, ThermalThrotter: 0, I2cProtocol: 116, PaddingConfig: 0, }, I2cControllerConfig_t { Enabled: 1, Speed: 0, SlaveAddress: 111, ControllerPort: 0, ControllerName: 105, ThermalThrotter: 0, I2cProtocol: 100, PaddingConfig: 0, }, I2cControllerConfig_t { Enabled: 1, Speed: 0, SlaveAddress: 103, ControllerPort: 0, ControllerName: 97, ThermalThrotter: 0, I2cProtocol: 105, PaddingConfig: 0, }, I2cControllerConfig_t { Enabled: 1, Speed: 0, SlaveAddress: 32, ControllerPort: 0, ControllerName: 97, ThermalThrotter: 0, I2cProtocol: 116, PaddingConfig: 0, }, I2cControllerConfig_t { Enabled: 1, Speed: 0, SlaveAddress: 77, ControllerPort: 0, ControllerName: 101, ThermalThrotter: 0, I2cProtocol: 109, PaddingConfig: 0, }, I2cControllerConfig_t { Enabled: 1, Speed: 0, SlaveAddress: 114, ControllerPort: 0, ControllerName: 121, ThermalThrotter: 0, I2cProtocol: 0, PaddingConfig: 0, }, ], GpioScl: 110, GpioSda: 0, FchUsbPdSlaveAddr: 0, I2cSpare: [ 0, ], VddGfxVrMapping: 0, VddSocVrMapping: 0, VddMem0VrMapping: 36, VddMem1VrMapping: 109, GfxUlvPhaseSheddingMask: 76, SocUlvPhaseSheddingMask: 175, VddciUlvPhaseSheddingMask: 0, MvddUlvPhaseSheddingMask: 1, GfxMaxCurrent: 36352, GfxOffset: 4, Padding_TelemetryGfx: 0, SocMaxCurrent: 0, SocOffset: 23, Padding_TelemetrySoc: 0, Mem0MaxCurrent: 0, Mem0Offset: 23, Padding_TelemetryMem0: 0, Mem1MaxCurrent: 0, Mem1Offset: -30, Padding_TelemetryMem1: 1, MvddRatio: 1323, AcDcGpio: 84, AcDcPolarity: 0, VR0HotGpio: 95, VR0HotPolarity: 0, VR1HotGpio: 77, VR1HotPolarity: 0, GthrGpio: 69, GthrPolarity: 0, LedPin0: 77, LedPin1: 0, LedPin2: 49, LedEnableMask: 0, LedPcie: 32, LedError: 0, LedSpare1: [ 1, 0, ], PllGfxclkSpreadEnabled: 1, PllGfxclkSpreadPercent: 0, PllGfxclkSpreadFreq: 110, DfllGfxclkSpreadEnabled: 1, DfllGfxclkSpreadPercent: 0, DfllGfxclkSpreadFreq: 67, UclkSpreadPadding: 1, UclkSpreadFreq: 110, FclkSpreadEnabled: 1, FclkSpreadPercent: 0, FclkSpreadFreq: 114, MemoryChannelEnabled: 7077999, DramBitWidth: 32, PaddingMem1: [ 0, 1, 0, ], TotalBoardPower: 97, BoardPowerPadding: 1, XgmiLinkSpeed: [ 110, 0, 0, 0, ], XgmiLinkWidth: [ 110, 0, 0, 0, ], XgmiFclkFreq: [ 0, 27870, 44890, 512, ], XgmiSocVoltage: [ 35840, 1, 0, 24, ], HsrEnabled: 0, VddqOffEnabled: 0, PaddingUmcFlags: [ 0, 0, ], UclkSpreadPercent: [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ], BoardReserved: [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ], MmHubPadding: [ 0, 0, 0, 0, 0, 0, 0, 102629376, ], }, }Edited by Umio YasunoThe same problem occurred on RX 6600.
That RX 6600 GPU is not connected via Thunderbolt...
Is it normal that we cannot get the correct link speed and link width from the DPM table (pp_dpm_pcie) ?$ cat /sys/class/drm/card0/device/pp_dpm_pcie 0: 2.5GT/s, 81Mhz 1: 2.5GT/s, 619MhzBisected: agd5f/linux@e701156c
After reverting agd5f/linux@e701156c,
pp_dpm_pciereports the correct link speed and link width.
Should I open a new issue?$ cat /sys/class/drm/card0/device/pp_dpm_pcie 0: 2.5GT/s, x1 81Mhz 1: 8.0GT/s, x8 619Mhz *Edited by Umio Yasuno@Umio-Yasuno Is this an intel system? Intel doesn't support PCIE DPM, though we may not be reporting the ultimate speed correctly.
No, it's AMD's system.
- CPU: Ryzen 5 5600G (up to PCIe Gen3 support, iGPU enabled)
- GPU: RX 6600 (up to PCIe Gen4 support, Running at Gen3x8)
Edited by Umio YasunoCan you have a try with this patch? 0001-drm-amd-Fix-logic-error-in-sienna_cichlid_update_pci.patch
assigned to @superm1
added 6000 dGPU Series label
mentioned in commit agd5f/linux@ade134dd
mentioned in commit agd5f/linux@2a1fe39a
mentioned in commit nouveau@d2894c4f
