- May 03, 2023
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Foz-DB Navi21: Totals from 62 (0.05% of 134864) affected shaders: VGPRs: 2464 -> 2440 (-0.97%) CodeSize: 332408 -> 324276 (-2.45%) MaxWaves: 1690 -> 1692 (+0.12%) Instrs: 62356 -> 60828 (-2.45%) Latency: 595723 -> 592554 (-0.53%) InvThroughput: 126106 -> 124241 (-1.48%) SClause: 2163 -> 2162 (-0.05%) Copies: 6392 -> 6226 (-2.60%); split: -2.94%, +0.34% Branches: 2295 -> 2298 (+0.13%) PreSGPRs: 2390 -> 2389 (-0.04%) PreVGPRs: 2139 -> 2117 (-1.03%); split: -1.08%, +0.05% Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Part-of: <mesa/mesa!22783>
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Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Part-of: <mesa/mesa!22783>
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This value depends on the per-sample value which can be unknown at compile time with graphics pipeline libraries. So we need to have this dynamic has well and pick the right value when generating the 3DSTATE_PS/3DSTATE_WM packet. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: d8dfd153 ("intel/fs: Make per-sample and coarse dispatch tri-state") Reviewed-by:
Emma Anholt <emma@anholt.net> Part-of: <!22728>
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David Heidelberg authored
Fixes: c5b3d488 ("mesa/main: make ffvertex output nir") Reviewed-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <mesa/mesa!22812>
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rf0 is affected by restrictions in some scenarios so we rather use a register that does not cause conflicts for scheduling. total instructions in shared programs: 12850958 -> 12848024 (-0.02%) instructions in affected programs: 331974 -> 329040 (-0.88%) helped: 2559 HURT: 201 Instructions are helped. total max-temps in shared programs: 2210893 -> 2210803 (<.01%) max-temps in affected programs: 1486 -> 1396 (-6.06%) helped: 96 HURT: 7 Max-temps are helped. total sfu-stalls in shared programs: 21975 -> 21965 (-0.05%) sfu-stalls in affected programs: 32 -> 22 (-31.25%) helped: 16 HURT: 6 Sfu-stalls are helped. total inst-and-stalls in shared programs: 12872933 -> 12869989 (-0.02%) inst-and-stalls in affected programs: 332036 -> 329092 (-0.89%) helped: 2560 HURT: 189 Inst-and-stalls are helped. total nops in shared programs: 305911 -> 303501 (-0.79%) nops in affected programs: 11215 -> 8805 (-21.49%) helped: 2131 HURT: 3 Nops are helped. Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!22797>
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Indeed, these references are not freed. For instance, this issue is triggered on an evergreen card with "piglit/bin/shader_runner tests/spec/arb_shader_atomic_counter_ops/execution/all_touch_test.shader_test -auto -fbo" while setting GALLIUM_REFCNT_LOG=refcnt.log. Fixes: 06993e4e ("r600: add support for hw atomic counters. (v3)") Signed-off-by:
Patrick Lerda <patrick9876@free.fr> Reviewed-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <mesa/mesa!22798>
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In-line with other files that generate source code Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <!22333>
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Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <!22333>
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Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <mesa/mesa!22333>
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Part-of: <mesa/mesa!22333>
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Reviewed-by:
Eric Engestrom <eric@igalia.com> Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <mesa/mesa!22333>
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Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <mesa/mesa!22333>
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Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <mesa/mesa!22333>
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Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <mesa/mesa!22333>
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Part-of: <!22333>
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Part-of: <mesa/mesa!22333>
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Otherwise a load of the cache won't load any of the objects in it! Fixes: 591da987 ("vulkan: Add a common VkPipelineCache implementation") Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!22700>
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On malloc failure, or more likely a passed in pDataSize < pipeline cache data size, we should return incomplete. Otherwise, vk_pipeline_cache_object_serialize will assertion fail about the start not being aligned. Closes: #8868 Fixes: 591da987 ("vulkan: Add a common VkPipelineCache implementation") Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!22700>
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- May 02, 2023
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Jesse Natalie authored
Part-of: <mesa/mesa!22810>
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Jesse Natalie authored
Part-of: <!22810>
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Jesse Natalie authored
Instead of re-computing all the same bits we already computed, just use the nir hash. Helps prevent missing a bit between the two. Part-of: <mesa/mesa!22810>
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Jesse Natalie authored
Part-of: <mesa/mesa!22810>
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Jesse Natalie authored
Previously this was only in the graphics path... where it does nothing, since D3D only supports wave size control for compute. Whoops. Fixes: db083070 ("dzn: Implement subgroup size control extension") Part-of: <mesa/mesa!22810>
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Indeed, the objects are not freed when the function returns NULL. "psurf->texture = tex;" is redundant with "pipe_resource_reference(&psurf->texture, tex);". For instance, this issue is triggered with "piglit/bin/ext_texture_array-compressed teximage pbo -fbo -auto" while setting GALLIUM_REFCNT_LOG=refcnt.log. Fixes: f3630548 ("crocus: initial gallium driver for Intel gfx 4-7") Signed-off-by:
Patrick Lerda <patrick9876@free.fr> Part-of: <mesa/mesa!22799>
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Android apps commonly use HWUI (a GLES-based UI framework provided by the system), that generally performs eglInitialize() before the app can do the same for its custom rendering needs. If an app is going to set VIRGL_DEBUG to enable case-by-case driver behaviors (e.g. experimental shader_sync option), it should be checked again during context creation. Signed-off-by:
Ryan Neph <ryanneph@google.com> Part-of: <mesa/mesa!22744>
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UBO descriptors can re-use the default descriptor when their upper bound is 64KiB, not the end of the buffer. Fixes dEQP-VK.memory.pipeline_barrier.host_write_uniform_buffer.1048576 Fixes: d34ac0a7 ("dzn: Re-design custom buffer descriptors") Part-of: <mesa/mesa!22805>
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This reverts commit 83a1b742. this is creating the pipeline layout, which is always required, not the dsl Fixes: 83a1b742 ("zink: don't create separate shader dsls if there are no bindings") Part-of: <mesa/mesa!22801>
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this could otherwise unbind a non-generated tcs if the tes had at some point generated a tcs cc: mesa-stable Part-of: <mesa/mesa!22801>
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Due to a copy-paste error, we asserted pipelineStageCreationFeedbackCount == 1 and wrote the stage feedback of the combined shader into the feedback of the first stage. This is fixed. Instead, we now write the precompilation feedback for each stage. This not ideal, but definitely an improvement. Part-of: <mesa/mesa!22100>
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Part-of: <mesa/mesa!22100>
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instead of pStages. Part-of: <mesa/mesa!22100>
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Part-of: <mesa/mesa!22100>
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Part-of: <mesa/mesa!22100>
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The purpose of this struct is to bundle per-stage information for ray-tracing pipelines. Part-of: <mesa/mesa!22100>
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Part-of: <mesa/mesa!22100>
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This patch adds functions to radv_pipeline_cache in order to cache serialized NIR shaders as opaque cache objects. Part-of: <mesa/mesa!22100>
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together with vk_raw_data_cache_object_ops and vk_raw_data_cache_object_create(). Part-of: <mesa/mesa!22100>
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We track fences in a global list and have a per context "current" fence which we randomly attach things to. If we take such a fence and emit it without also creating a new fence for future tasks we can get out of sync leading to random failures. Some of our queries could trigger such cases and even though this issues appears to be triggered by the MT rework, I'm convinced that this was only made more visible by those fixes and we had this bug lurking for quite a while. Closes: mesa/mesa#7429 Fixes: df0a4d02 ("nvc0: make state handling race free") Signed-off-by:
Karol Herbst <git@karolherbst.de> Acked-by:
M Henning <drawoc@darkrefraction.com> Part-of: <mesa/mesa!22722>
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Update crosvm, virglrenderer and bindgen-cli to their latest version on time. Signed-off-by:
Corentin Noël <corentin.noel@collabora.com> Reviewed-by:
Yiwei Zhang <zzyiwei@chromium.org> Part-of: <mesa/mesa!22712>
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Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Part-of: <!22793>
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