"README.rst" did not exist on "6aade42111304a8c79fe515bbe3286631bd70d37"
- Apr 14, 2023
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Explains some of hardware units referenced throughout the driver. Signed-off-by:
i509VCB <git@i509.me> Part-of: <!22200>
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Signed-off-by:
Karol Herbst <kherbst@redhat.com> Reviewed-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <!19712>
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Signed-off-by:
Karol Herbst <kherbst@redhat.com> Reviewed-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!19712>
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Signed-off-by:
Karol Herbst <kherbst@redhat.com> Reviewed-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!19712>
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At the moment it's an all or nothing. A driver supporting fine-grained system SVM can enable it in order to get full SVM support. Lower levels could be emulated by userptrs and placing the bo at the same locations in the GPU's VM as well, but that would require reworking quite a bit on the drivers side. For now supporting mmu_notifiers on the kernel side is the only way of getting SVM support with Rusticl. The only driver having the gallium bits wired up atm is Nouveau, but I suspect it shouldn't be all to hard for iris and radeonsi as well. Signed-off-by:
Karol Herbst <kherbst@redhat.com> Part-of: <!19712>
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Signed-off-by:
Karol Herbst <kherbst@redhat.com> Part-of: <mesa/mesa!19712>
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The old code didn't consider a few cases where we could just map resources located in system RAM. Signed-off-by:
Karol Herbst <kherbst@redhat.com> Part-of: <!19712>
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Signed-off-by:
Karol Herbst <kherbst@redhat.com> Reviewed-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!19712>
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Signed-off-by:
Karol Herbst <kherbst@redhat.com> Reviewed-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!19712>
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no longer used Part-of: <mesa/mesa!22493>
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this feels dumb, but I can't think of a simpler way to do it that would more accurately handle deletion while also guaranteeing pool longevity Fixes: 7da78ffb ("zink: create/use query pools dynamically") Part-of: <mesa/mesa!22493>
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no functional changes Part-of: <mesa/mesa!22493>
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this is never accessed from threads anymore and hasn't been for a long time Part-of: <mesa/mesa!22493>
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Closes: mesa/mesa#8756 Signed-off-by:
Thong Thai <thong.thai@amd.com> Reviewed-by:
Sil Vilerino <sivileri@microsoft.com> Reviewed-by:
Ruijing Dong <ruijing.dong@amd.com> Reviewed-by:
Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <mesa/mesa!22422>
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Signed-off-by:
Thong Thai <thong.thai@amd.com> Reviewed-by:
Ruijing Dong <ruijing.dong@amd.com> Reviewed-by:
Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <mesa/mesa!22422>
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Signed-off-by:
Thong Thai <thong.thai@amd.com> Reviewed-by:
Sil Vilerino <sivileri@microsoft.com> Reviewed-by:
Ruijing Dong <ruijing.dong@amd.com> Reviewed-by:
Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <mesa/mesa!22422>
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Closes: mesa/mesa#3833 Part-of: <mesa/mesa!22454>
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Part-of: <mesa/mesa!22454>
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This uses CD3DX12_PIPELINE_STATE_STREAM3 from d3dx12_pipeline_state_stream.h and gives us access to newer D3D12 features. Part-of: <mesa/mesa!22454>
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Part-of: <mesa/mesa!22454>
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Part-of: <mesa/mesa!22454>
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Anv is trying to rely on the stages put into the library graphics state. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <!22460>
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this is almost certainly a failure case, but drivers still shouldn't get xfb info if there are no outputs affects: spec@glsl-1.50@execution@interface-blocks-api-access-members cc: mesa-stable Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!22448>
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Replace 'unsignalled' with 'ready' to simplify logic. Remove needless !! in !!(a > b) expressions. Remove some casting. Use MIN2() macro. Add const qualifiers. Declare loop vars in loops. Signed-off-by:
Brian Paul <brianp@vmware.com> Part-of: <mesa/mesa!22464>
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This returned size was never used by the callers. Signed-off-by:
Brian Paul <brianp@vmware.com> Part-of: <mesa/mesa!22464>
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Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!22478>
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- Apr 13, 2023
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This packet is supported on GFX6 too, its name should relect that. Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <!22406>
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Also don't check whether chaining is enabled in radv_queue, the winsys will take care of that anyway. Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!22406>
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GFX6 supports IB chaining since the PFP firmware version 20. Note that the very first amdgpu firmware for GFX6 already had version 29, so we can assume that all GPUs supported by RADV have this feature. Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!22406>
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GFX6 has the same problem as GFX7 here. Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!22406>
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These used to guard against chaining on GFX6 and on HW IP types that don't support chaining, but these things are now guarded elsewhere and these assertions are no longer necessary. Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!22406>
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Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!22432>
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Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!22432>
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Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!22432>
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Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!22432>
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Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!22432>
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Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!22432>
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Reviewed-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!22432>
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Reviewed-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!22432>
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