- Feb 02, 2022
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Also assert that nobody actually needs to chain an SDMA IB because we have not implemented non-PKT3 chaining. Fixes: ef40f2cc ("radv/amdgpu: Fix handling of IB alignment > 4 words.") Closes: mesa/mesa#5923 Tested-by: Mike Lothian <mike@fireburn.co.uk> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!14781>
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Emma Anholt authored
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Part-of: <mesa/mesa!14725>
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Emma Anholt authored
Fixes: #5921 Part-of: <mesa/mesa!14725>
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Enable setting ANV_EXPERIMENTAL_NV_MESH_SHADER=1 environment variable. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <!13662>
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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <mesa/mesa!13662>
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Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!13662>
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Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!13662>
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Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!13662>
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Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!13662>
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Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!13662>
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Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!13662>
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Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!13662>
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The Mesh pipeline is implemented as a variant of the regular (primitive) Graphics Pipeline. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <mesa/mesa!13662>
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Use minimum values for the properties. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <mesa/mesa!13662>
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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!13662>
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And corresponding value in XML. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <mesa/mesa!13662>
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This is a nontrivial chunk of code that makes for a nice dis/assembler test case (and caught a bug already...). Add it to the observatory. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!14833>
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Noticed in a program using ARM_shader_framebuffer_fetch. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!14833>
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The swizzle handling in ISA.xml was broken in a bunch of place. Now that we've fixed these issues, let's add tons of tests to validate. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!14833>
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Instructions like V2S8_TO_V2S16 need a special 4-bit special selecting any two bytes. The definition is the same as Bifrost. Let's call this a half-swizzle since we need a name, and it is indeed half a swizzle... Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!14833>
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Matches Bifrost, too. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!14833>
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The lane select is in bit 28, this is covered by the "16-bit swizzle" mode. However, the source type isn't inferred from the name in valhall.py, so explicitly annotate the source as 16-bit. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!14833>
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The lanes are at bit 28 and bit 26 respectively. This matches the 16-bit "swizzle" encoding. In general the handling of widens/swizzles/lane/lanes on Valhall is rather confused but... one problem at a time. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!14833>
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Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!14833>
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Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!14833>
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For parity with Bifrost. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!14833>
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Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!14833>
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Per primitive & attachment shading rate support added. v2: Rebase on KHR_dynamic_rendering Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!13739>
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For instance, the current code in genX_cmd_buffer.c assumes that the depth/stencil attachments & resolves will be at the end of all attachments, but that won't be the case anymore with fragment rate shading. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!13739>
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v2: Use new helper to check if stage supports variable shading rate setting v3: Update comment & iterate backward (Caio) Apply only to relevant platforms (Lionel) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <!13739>
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!13739>
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Rework: * Jason: Modernize brw_nir_lower_shading_rate_output: 1. Use nir_shader_instructions_pass() 2. Use *_imm builder helpers. 3. Use nir_intrinsic_base() instead of ->const_index[0] v2: Also lower loads (Caio) v3: Update stage check to trigger lowering (Caio) v4: Assert on != MESH (Caio) v5: Fixup instruction insertion (Caio) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!13739>
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v2: add (y >= x->bit_size) condition (Caio) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!13739>
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <mesa/mesa!13739>
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Those surfaces are used as attachment to rendering passes and describe the rate of coarse pixel shading for the pass. v2: Move CPB_BIT tile filtering to isl_gfx125_filter_tiling() (Nanley) v3: Drop unused macro (Nanley) s/isl_to_gen/isl_encode/ (Nanley) Remove pitch alignment 128B constraint already covered by tiling (Nanley) Move some asserts together (Nanley) v4: Disable miptail for now (Nanley) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <mesa/mesa!13739>
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DG2 introduces per primitive coarse pixel settings (in stages preceding the PS shader) and also a control surface specifying the rate at through the resulting surface. v2: update comment (Caio) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!13739>
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!13739>
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v2: Make genxml look more like BSpec (Caio) Fixup X_Focal/Y_Focal entries (Caio) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!13739>
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <!13739>
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Recursive "loops" tend to be more difficult to follow and understand. Additionally iterative approach should be nicer for compiler. (Less to allocate on stack and easier to optimize) Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!13226>
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