- May 17, 2018
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Juan A. Suárez authored
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
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Juan A. Suárez authored
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
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- May 15, 2018
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Otherwise the build fails with an undefined reference to clang::FrontendTimesIsEnabled. Bugzilla: https://bugs.freedesktop.org/106209 Cc: Jan Vesely <jan.vesely@rutgers.edu> Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org> Acked-by: Jan Vesely <jan.vesely@rutgers.edu> Tested-by: Aaron Watry <awatry@gmail.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> (cherry picked from commit b691d919)
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The hardware always interprets the alpha as unsigned and fixing it in the shader is going to add unacceptable overheads. CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480 Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit f944a599)
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Pre-Vega HW always interprets the alpha for this format as unsigned, so we have to implement a fixup to do the sign correctly for signed formats. v2: Improve indexing mess. CC: 18.0 <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480 Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (Backport of 3d4d388e "radv: Fix up 2_10_10_10 alpha sign.")
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radeonsi could pass them through but the enum changed between Gallium and Vulkan, so we have to translate. In progress I made the register defines a bit more readable. CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100430 Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit dd102405) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/amd/vulkan/radv_pipeline.c
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I don't think the hw resolve path can't handle multi-layer images. This fixes all the: dEQP-VK.renderpass.multisample_resolve.layers_* tests on my VI card. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: <mesa-stable@lists.freedesktop.org> (cherry picked from commit 5978d54a)
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This path should iterate across all layers, I've some ideas for doing this in a single pass, but this is simpler for now. This passes the tests because we don't use the fragment path unless we have DCC, and we don't have DCC on layered images. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: <mesa-stable@lists.freedesktop.org> (cherry picked from commit 98dbaa44)
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Juan A. Suárez authored
stable: The commit requires earlier commits ab0e625a and 62510846 which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
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Fixes memory leak on module unload. CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 58272c1a)
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Juan A. Suárez authored
stable: The commit fixes earlier commit d07466fe which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
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Juan A. Suárez authored
stable: The commit fixes earlier commit d5f42f96 which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
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From the bspec docs for "Indirect State Pointers Disable": "At the completion of the post-sync operation associated with this pipe control packet, the indirect state pointers in the hardware are considered invalid" So the ISP disable is a post-sync type of operation which means that it should be combined with a CS stall. Without this, the simulator throws an error. Fixes: 766d801c "anv: emit pixel scoreboard stall before ISP disable" Fixes: f536097f "i965: require pixel scoreboard stall prior to ISP disable" Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit a8a740f2)
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We want to make sure that all indirect state data has been loaded into the EUs before disable the pointers. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> Fixes: 78c125af ("anv/gen10: Ignore push constant packets during context restore.") (cherry picked from commit 766d801c)
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Invalidating the indirect state pointers might affect a previously scheduled & still running 3DPRIMITIVE (causing page fault). So stall on pixel scoreboard before that. v2: Fix compile issue :( v3: Stall on pixel scoreboard v4: Drop the post sync operation (Lionel) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> Fixes: ca19ee33 ("i965/gen10: Ignore push constant packets during context restore.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106243 (cherry picked from commit f536097f)
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Fixes memory leak on module unload. v2: Use util_hash_table helper function CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> (cherry picked from commit 45dfa6f4)
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CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> (cherry picked from commit d146768d)
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If you have an indirect access to a constant buffer on r600/eg use a vertex fetch in the shader. However apps have expected behaviour on those out of bounds accessess (even if illegal). If the constants were being uploaded as part of a larger upload buffer, we'd set the range of allowed access to a lot larger than required so apps would get values back from other parts of the upload buffer instead of the expected out of bounds access. This fixes rendering bugs in Trine and Witcher 1, thanks to iive for nagging me effectively until I figured it out :-) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91808 Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Roland Scheidegger <sroland@vmware.com> (cherry picked from commit ce027ac5)
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Out of tree builds can try to write into a directory that doesn't exist yet: | Traceback (most recent call last): | File "../../../mesa-18.0.2/src/intel/vulkan/anv_icd.py", line 46, in <module> | with open(args.out, 'w') as f: | IOError: [Errno 2] No such file or directory: 'vulkan/intel_icd.x86_64.json' | Makefile:4882: recipe for target 'vulkan/intel_icd.x86_64.json' failed Add missing MKDIR_GEN calls to solve this. Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit 1755654d)
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CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (cherry picked from commit 5ac16ed0)
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CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 0783399d)
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Juan A. Suárez authored
stable: The commit requires earlier commit ba79a90f which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
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CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit a9e4be92)
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CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit a1e8fcce)
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Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit ea1fff44)
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We used to only initialize BLORP on Gen6+. When we added it on Gen4-5, we forgot to destroy it unconditionally. Fixes: 752d7af7 (i965: Add blorp support for gen4-5) Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit 2dc29e09) Squashed with: i965: silence unused variable Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 2dc29e09 ("i965: Don't leak blorp on Gen4-5.") Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> (cherry picked from commit 3853f1c6)
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It is needed to destroy the v vector in scalar_argument Fixes memory leaks on parameter set/bind. v2: Drop redundant sclara_argument destructor Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Francisco Jerez <currojerez@riseup.net> (cherry picked from commit 2f1ad72a)
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This behaviour was changed in 1e5b09f4. The commit message for that says it is just a “tidy up” so my assumption is that the behaviour change was a mistake. It’s a little hard to decipher looking at the diff, but the previous code before that patch was: if (builtin == SpvBuiltInFragCoord || builtin == SpvBuiltInSamplePosition) nir_var->data.origin_upper_left = b->origin_upper_left; if (builtin == SpvBuiltInFragCoord) nir_var->data.pixel_center_integer = b->pixel_center_integer; After the patch the code was: case SpvBuiltInSamplePosition: nir_var->data.origin_upper_left = b->origin_upper_left; /* fallthrough */ case SpvBuiltInFragCoord: nir_var->data.pixel_center_integer = b->pixel_center_integer; break; Before the patch origin_upper_left affected both builtins and pixel_center_integer only affected FragCoord. After the patch origin_upper_left only affects SamplePosition and pixel_center_integer affects both variables. This patch tries to restore the previous behaviour by changing the code to: case SpvBuiltInFragCoord: nir_var->data.pixel_center_integer = b->pixel_center_integer; /* fallthrough */ case SpvBuiltInSamplePosition: nir_var->data.origin_upper_left = b->origin_upper_left; break; This change will be important for ARB_gl_spirv which is meant to support OriginLowerLeft. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Fixes: 1e5b09f4 "spirv: Tidy some repeated if checks..." (cherry picked from commit e17d0ccb)
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Found by inspection, so I made a piglit test too. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit f2db3be6)
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Similar to swap_available path send invalidate to the driver because egl/X11 is not watching for for server's invalidate events. The dri2_copy_region path is trigerred when server supports DRI2 version minor 1. Tested with piglit egl tests for regression. V2: Move invalidate from dri2_copy_region to swap_buffer common. Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Deepak Rawat <drawat@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com> (cherry picked from commit 9a21c961)
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16-bit immediates need to replicate the 16-bit immediate value in both words of the 32-bit value. This needs to be careful to avoid sign-extension, which the previous implementation was not handling properly. For example, with the previous implementation, storing the value -3 would generate imm.d = 0xfffffffd due to signed integer sign extension, which is not correct. Instead, we should cast to uint16_t, which gives us the correct result: imm.ud = 0xfffdfffd. We only had a couple of cases hitting this path in the driver until now, one with value -1, which would work since all bits are one in this case, and another with value -2 in brw_clip_tri(), which would hit the aforementioned issue (this case only affects gen4 although we are not aware of whether this was causing an actual bug somewhere). v2: Make explicit uint32_t casting for left shift (Jason Ekstrand) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "18.0 18.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit f0e6dace)
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From Intel Skylake PRM, vol 07, "Immediate" section (page 768): "For a word, unsigned word, or half-float immediate data, software must replicate the same 16-bit immediate value to both the lower word and the high word of the 32-bit immediate field in a GEN instruction." This fixes the int16/uint16 negate and abs immediates that weren't taking into account the replication in lower and upper words. v2: Integer cases are different to Float cases. (Jason Ekstrand) Included reference to PRM (Jose Maria Casanova) v3: Make explicit uint32_t casting for left shift (Jason Ekstrand) Split half float implementation. (Jason Ekstrand) Fix brw_abs_immediate (Jose Maria Casanova) Cc: "18.0 18.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 2a76f03c)
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Juan A. Suárez authored
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
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- May 07, 2018
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Previously before fb077b07, the LOD parameter was being used in place of the sample index, which would only copy the first sample to all samples in the destination image. After that multisample image copies wouldn't copy anything from my observations. This fixes some copy_and_blit CTS tests. v3.1: - set lod to 0 for nir_txf_ms (Samuel) v2: - use GLSL_SAMPLER_DIM_MS instead of 2D (Samuel) - updated commit description (Samuel) Fix this properly by copying each sample in a separate radv_CmdDraw and using a pipeline with the correct rasterizationSamples for the destination image. Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 97d57ef9)
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Juan A. Suárez authored
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
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Juan A. Suárez authored
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
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Juan A. Suárez authored
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
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- May 02, 2018
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Previous bit-fields assignments are incorrect and will result certain mpeg4 decode failed due to wrong flag values. This patch fixes these assignments. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> (cherry picked from commit deba56ac)
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Both the internal documentation and the results of testing this in the CI suggest that this is unnecessary. Add the fixes tag because this reduces an internal benchmark's startup time by about 17 seconds (reported by Eero). Fixes: 710b1d2e "i965/tex_image: Flush certain subnormal ASTC channel values" Tested-by: Eero Tamminen <eero.t.tamminen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 3e56e464)
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Only count color attachments twice if resolves are used, also account for the depth stencil attachment if present. Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit d8db5986)
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