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So the main thing to do here is to upstream a single MIPI lane configuration to the B+W - monochrome sensor.
Intel has done a bunch of work getting sensors upstream to their credit. Intel's typical configuration for monochrome sensors is two data lane mode, whereas qcom does 1 lane.
In a practical sense its not a big change but, first step here is to locate the relevant init sequence and upstream it + necessary driver description.
Okay, here are some additional information from your valuable research so far :-)
The B+W sensor is ov9734. As the datasheet describes it has just single MIPI line.
The sensor has XSHUTDN pin that is used for power down and reset (active low with internal pull down resistor)
There's additional pin SID that determines the I2C address (SCCB address selection), however based on your research the address seems to be 0x36. There's also a note: SID pin should be pulled low for device address 0x6C and pulled high for device address 0x20.
The I2C pins correspond to the signals cci_i2c_sda2/cci_i2c_scl2 on cci1_i2c0
The regulators for the sensor are: vreg_l3q, vreg_l5q and vreg_l1q providing dovdd, avdd and dvdd respectively
The input clock for the sensor is driven by MCLK4 signal
The sensor was upstreamed by Intel and can be found under drivers/media/i2c/ov9734.c
Since the data from the sensor will be RAW it will need processing right> But the software ISP should be enough. There's no need for the Spectra IDSP though offloading to hardware would be preferred.
Would you happen to know which pins are dedicated to the IR LED? Does it use PWM through some dedicated peripheral on the SoC or it's simply ON/OFF for the GPIO?
Is it also safe to play with the PWM? As eyes are sensitive to light there should be some additional HW that would ensure that the duty cycle of the PWM is within hygienic limits.
Also as it should be using structured light do we know what kind of pattern mask is on top of the IR LED?
It must have been calibrated during manufacturing and the reference image against plain surface stored somewhere.
So how exactly are the two cameras connected? Is there some mux that switches which MIPI lane(s) is connected to the csiphy? Or do the sensors have a dedicated port with dedicated lanes for each sensor?
Also defining the other cci interface for the ov9734 sensor causes these error messages in the kernel log:
[ 2.946498] sc8280xp-tlmm f100000.pinctrl: pin GPIO_123 already requested by 988000.serial; cannot claim for ac4b000.cci[ 2.946501] sc8280xp-tlmm f100000.pinctrl: error -EINVAL: pin-123 (ac4b000.cci)[ 2.946504] sc8280xp-tlmm f100000.pinctrl: error -EINVAL: could not request pin 123 (GPIO_123) from group gpio123 on device f100000.pinctrl[ 2.946506] i2c-qcom-cci ac4b000.cci: Error applying setting, reverse things back[ 2.946700] i2c-qcom-cci ac4c000.cci: Found 19200000 cci clk rate while 37500000 was expected
Based on the sc8280xp.dtsi the camss has 4 interfaces csiphy{0,1,2,3}.