- Mar 11, 2025
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Kenneth Graunke authored
The documentation for 3DSTATE_URB_HS has 0 as the minimum number of HS URB entries for all platforms. See BSpecs 32162, 47137, 56271 for Gfx6-11, Xe, and Xe2-3, respectively. This should silence warnings about our device info field not matching the hwconfig tables. Notably, nothing in our drivers currently uses this value so it cannot have a functional impact. Fixes: 4064b554 ("intel/dev: reduce warning noise from urb settings") Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!33764>
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Kenneth Graunke authored
Used in exactly one place in elk. Off to live there. Reviewed-by:
Dylan Baker <dylan.c.baker@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!33764>
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Kenneth Graunke authored
This is only needed for original 965G/GM clipper code, which only exists in the legacy compiler. Send it off to live with the elk. Reviewed-by:
Dylan Baker <dylan.c.baker@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!33764>
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Kenneth Graunke authored
This is used in exactly one place in crocus, which already has a comment indicating that this code is needed for original Gfx4 hardware. Just replace that with a verx10 == 40 check. Reviewed-by:
Dylan Baker <dylan.c.baker@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!33764>
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Kenneth Graunke authored
This is used by a single place in ISL only for sanity checking the decisions it has already made. The knowledge is already all centralized in ISL these days, so we don't need a device info bit. Reviewed-by:
Dylan Baker <dylan.c.baker@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!33764>
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Kenneth Graunke authored
This code is a lot of mess for no real benefit. It's existed since the dawn of isl, and serves to let you optimize out a single check in release builds for Ironlake and Sandybridge systems. All other uses are for asserts, which already get compiled out in release mode. Reviewed-by:
Dylan Baker <dylan.c.baker@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!33764>
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Kenneth Graunke authored
This code, since the dawn of time, has had a redundant check for gen5-6 separate stencil in the final else clause: } else if (doing separate stencil on gen5-6) { return compact } else { if (doing separate stencil on gen5-6) return compact ... } We can eliminate that one. The else clause then has a single if, so it can be folded into the "else if" ladder alongside the others. Reviewed-by:
Dylan Baker <dylan.c.baker@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!33764>
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- Mar 10, 2025
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If an image gets created with unsupported parameters (which is a pretty complex thing to check), it's probably better to just return an error rather than panic, especially since Rust panics happen even in release builds. Reviewed-by:
Mel Henning <mhenning@darkrefraction.com> Part-of: <mesa/mesa!33990>
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They're so different that sharing the code really wasn't buying us anything. It's way easier to read if the two are separated. Reviewed-by:
Mel Henning <mhenning@darkrefraction.com> Part-of: <mesa/mesa!33990>
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Compositors sometime try to import BOs with lower alignments than 128B. This seems particularly common in the case of cursor images but it can also happen on other BOs allocated by the old nouveau GL driver. As long as we avoid rendering to them (which NVK will do), the texture/image hardware is fine as long as they're at least 32B-aligned. Panicing in this case isn't very nice to compositors. Backport-to: 25.0 Reviewed-by:
Mel Henning <mhenning@darkrefraction.com> Part-of: <mesa/mesa!33990>
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We can do this by just enabling the fall-back path whenever we detect something that's not nicely aligned. Backport-to: 25.0 Reviewed-by:
Mel Henning <mhenning@darkrefraction.com> Part-of: <mesa/mesa!33990>
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This may not be true if it comes from the nouveau GL driver. Reviewed-by:
Mel Henning <mhenning@darkrefraction.com> Part-of: <mesa/mesa!33990>
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When importing libdrm_radeon code [1][2] it was somehow missed that what libdrm has in one r600_pci_ids.h, Mesa has split into r600_pci_ids.h and radeonsi_pci_ids.h. So, devices with ids from radeonsi_pci_ids.h were not considered valid for radeon_surface_manager_new. This commit changes that, thus fixing radeonsi for these devices. [1] commit 1299f5c5 [2] commit 3aa7497c Fixes: 1299f5c5 Signed-off-by:
Ivan A. Melnikov <iv@altlinux.org> Part-of: <mesa/mesa!33940>
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It was never sync and never will be. Luckily we can just remove it now. Part-of: <mesa/mesa!33775>
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Part-of: <mesa/mesa!33775>
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Part-of: <mesa/mesa!33775>
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Indicate that the CSO can actually be shared across pipe_contexts. Part-of: <mesa/mesa!33775>
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This removes one loop, also will allow us to cache the device builds in the queue to optimize binding compute states. Part-of: <mesa/mesa!33775>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <!33901>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!33901>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!33901>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <!33901>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!33901>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!33901>
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for indirect GS, do it in the indirect kernel (not the pre-GS) for direct, do it on the host (not the pre-GS) we don't want pre-GS. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <!33901>
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otherwise, an atomic suffices for the count shader. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <!33901>
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we'd CSE but meh Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!33901>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <!33901>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!33901>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <!33901>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <!33901>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!33901>
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Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <!33901>
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to make it easier for people (especially newcomers to the project) to add review tags, we need a database mapping gitlab usernames to author names & emails. that way, if someone just comments "rb" or whatever, there's a direct way to look that up. this comimt adds a list of current contributors with the following methodology: 1. first, I grabbed all names + emails of recent authors, with mailmap applied, as proxy for active contributors: $ git log --since=2025-01-01 --pretty='%aN,%aE,'|sort | uniq 2. then, I scraped usernames via the gitlab api attempting to match by name. I don't want to hammer the gitlab api too much which is why I tried to keep the list in #1 as small as possible. import gitlab import subprocess import tempfile import sys import urllib.request import csv gl = gitlab.Gitlab('https://gitlab.freedesktop.org ', private_token=...) names = {} with open('dump.csv') as csvfile: spamreader = csv.reader(csvfile) for row in spamreader: if len(row) == 3: names[row[0]] = row[1] for name in names: users = gl.users.list(search=name) print(', '.join([name, names[name]] + [u.username for u in users])) 3. finally, I fixed up various data issues by hand. there were cases of both people with multiple usernames (I tried to pick the one that's actually in use), and people whose name on their profile does not match the name in their commits (I tried to determine the username from searching gitlab manually, but dropped a number of such authors when it was nontrivial to figure out. I am a regular reviewer across the tree so if I don't recognize your name you're probably not that active, sorry.) Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Mel Henning <mhenning@darkrefraction.com> Part-of: <mesa/mesa!33896>
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..or "the one where Alyssa gets jealous by b4". Those of us who have stuck around a while have a habit of just commenting "rb" or "ab" on MRs. which raises the question for everyone else of what name/email to use. I've personally built up a collection of 36 (!!) different shell aliases to apply different people's trailers. I think other people do similarly. This calls for better tooling. This patch adds a little script for applying review trailers given a fuzzy match on the reviewer's name. I recommend contributors alias it to something like `mrb`, then you can do things like: mrb alyssa mrb -a faith to add a review tag for me or an acked-by tag for Faith. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Mel Henning <mhenning@darkrefraction.com> Part-of: <mesa/mesa!33896>
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Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!33957>
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The C++ one is more used, so let that one remain. These data structures are not used from C sources anymore. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!33957>
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It is expected that inputs and prefetches are always in the first block. However, ir3_create_empty_preamble would create blocks before the first one, leaving inputs after the preamble. This causes issues with (probably among others) spilling/RA where precolored inputs could illegally reuse the spill base register. Fixes RA validation failures on a7xx for dEQP-VK.ray_query.multiple_ray_queries.vertex_shader Signed-off-by:
Job Noorman <jnoorman@igalia.com> Fixes: f3026b3d ("ir3: add some preamble helpers") Part-of: <mesa/mesa!33977>
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Otherwise the encoder can read a stale value and make internal nodes point into leaf space (if 0 is read). Cc: mesa-stable Part-of: <!33985>
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For empty BVHs we shouldn't emit any leaf nodes, but there is one invocation to encode the root node. Guard leaf node encoding so that invocation doesn't try writing any leaves. Cc: mesa-stable Part-of: <!33985>
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