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with 127 additions and 439 deletions
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
View file @ 3e3fcd29
......@@ -2002,8 +2002,8 @@ void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work)
if (adev->kfd.init_complete) {
WARN_ON_ONCE(!adev->gfx.kfd_sch_inactive[idx]);
WARN_ON_ONCE(adev->gfx.kfd_sch_req_count[idx]);
amdgpu_amdkfd_start_sched(adev, idx);
adev->gfx.kfd_sch_inactive[idx] = false;
amdgpu_amdkfd_start_sched(adev, idx);
adev->gfx.kfd_sch_inactive[idx] = false;
}
}
mutex_unlock(&adev->enforce_isolation_mutex);
......
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
View file @ 3e3fcd29
......@@ -40,18 +40,25 @@
#include "amdgpu_connectors.h"
#include "amdgpu_display.h"
#include "dce_v6_0.h"
#include "sid.h"
#include "bif/bif_3_0_d.h"
#include "bif/bif_3_0_sh_mask.h"
#include "oss/oss_1_0_d.h"
#include "oss/oss_1_0_sh_mask.h"
#include "gca/gfx_6_0_d.h"
#include "gca/gfx_6_0_sh_mask.h"
#include "gca/gfx_7_2_enum.h"
#include "gmc/gmc_6_0_d.h"
#include "gmc/gmc_6_0_sh_mask.h"
#include "dce/dce_6_0_d.h"
#include "dce/dce_6_0_sh_mask.h"
#include "gca/gfx_7_2_enum.h"
#include "dce_v6_0.h"
#include "si_enums.h"
static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
......@@ -59,31 +66,31 @@ static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
static const u32 crtc_offsets[6] =
{
SI_CRTC0_REGISTER_OFFSET,
SI_CRTC1_REGISTER_OFFSET,
SI_CRTC2_REGISTER_OFFSET,
SI_CRTC3_REGISTER_OFFSET,
SI_CRTC4_REGISTER_OFFSET,
SI_CRTC5_REGISTER_OFFSET
CRTC0_REGISTER_OFFSET,
CRTC1_REGISTER_OFFSET,
CRTC2_REGISTER_OFFSET,
CRTC3_REGISTER_OFFSET,
CRTC4_REGISTER_OFFSET,
CRTC5_REGISTER_OFFSET
};
static const u32 hpd_offsets[] =
{
mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
HPD0_REGISTER_OFFSET,
HPD1_REGISTER_OFFSET,
HPD2_REGISTER_OFFSET,
HPD3_REGISTER_OFFSET,
HPD4_REGISTER_OFFSET,
HPD5_REGISTER_OFFSET
};
static const uint32_t dig_offsets[] = {
SI_CRTC0_REGISTER_OFFSET,
SI_CRTC1_REGISTER_OFFSET,
SI_CRTC2_REGISTER_OFFSET,
SI_CRTC3_REGISTER_OFFSET,
SI_CRTC4_REGISTER_OFFSET,
SI_CRTC5_REGISTER_OFFSET,
CRTC0_REGISTER_OFFSET,
CRTC1_REGISTER_OFFSET,
CRTC2_REGISTER_OFFSET,
CRTC3_REGISTER_OFFSET,
CRTC4_REGISTER_OFFSET,
CRTC5_REGISTER_OFFSET,
(0x13830 - 0x7030) >> 2,
};
......@@ -1389,13 +1396,13 @@ static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
static const u32 pin_offsets[7] =
{
(0x1780 - 0x1780),
(0x1786 - 0x1780),
(0x178c - 0x1780),
(0x1792 - 0x1780),
(0x1798 - 0x1780),
(0x179d - 0x1780),
(0x17a4 - 0x1780),
AUD0_REGISTER_OFFSET,
AUD1_REGISTER_OFFSET,
AUD2_REGISTER_OFFSET,
AUD3_REGISTER_OFFSET,
AUD4_REGISTER_OFFSET,
AUD5_REGISTER_OFFSET,
AUD6_REGISTER_OFFSET,
};
static int dce_v6_0_audio_init(struct amdgpu_device *adev)
......@@ -2954,22 +2961,22 @@ static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
switch (crtc) {
case 0:
reg_block = SI_CRTC0_REGISTER_OFFSET;
reg_block = CRTC0_REGISTER_OFFSET;
break;
case 1:
reg_block = SI_CRTC1_REGISTER_OFFSET;
reg_block = CRTC1_REGISTER_OFFSET;
break;
case 2:
reg_block = SI_CRTC2_REGISTER_OFFSET;
reg_block = CRTC2_REGISTER_OFFSET;
break;
case 3:
reg_block = SI_CRTC3_REGISTER_OFFSET;
reg_block = CRTC3_REGISTER_OFFSET;
break;
case 4:
reg_block = SI_CRTC4_REGISTER_OFFSET;
reg_block = CRTC4_REGISTER_OFFSET;
break;
case 5:
reg_block = SI_CRTC5_REGISTER_OFFSET;
reg_block = CRTC5_REGISTER_OFFSET;
break;
default:
DRM_DEBUG("invalid crtc %d\n", crtc);
......
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
View file @ 3e3fcd29
......@@ -28,19 +28,30 @@
#include "amdgpu_gfx.h"
#include "amdgpu_ucode.h"
#include "clearstate_si.h"
#include "si.h"
#include "sid.h"
#include "bif/bif_3_0_d.h"
#include "bif/bif_3_0_sh_mask.h"
#include "oss/oss_1_0_d.h"
#include "oss/oss_1_0_sh_mask.h"
#include "gca/gfx_6_0_d.h"
#include "gca/gfx_6_0_sh_mask.h"
#include "gca/gfx_7_2_enum.h"
#include "gmc/gmc_6_0_d.h"
#include "gmc/gmc_6_0_sh_mask.h"
#include "dce/dce_6_0_d.h"
#include "dce/dce_6_0_sh_mask.h"
#include "gca/gfx_7_2_enum.h"
#include "si_enums.h"
#include "si.h"
#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
......
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
View file @ 3e3fcd29
......@@ -528,8 +528,9 @@ static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev,
bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT;
is_system = (bo->tbo.resource->mem_type == TTM_PL_TT) ||
(bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT);
is_system = bo->tbo.resource &&
(bo->tbo.resource->mem_type == TTM_PL_TT ||
bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT);
if (bo && bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
*flags |= AMDGPU_PTE_DCC;
......
drivers/gpu/drm/amd/amdgpu/si.c
View file @ 3e3fcd29
......@@ -1124,41 +1124,41 @@ static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
{mmCP_STALLED_STAT3},
{GB_ADDR_CONFIG},
{MC_ARB_RAMCFG},
{GB_TILE_MODE0},
{GB_TILE_MODE1},
{GB_TILE_MODE2},
{GB_TILE_MODE3},
{GB_TILE_MODE4},
{GB_TILE_MODE5},
{GB_TILE_MODE6},
{GB_TILE_MODE7},
{GB_TILE_MODE8},
{GB_TILE_MODE9},
{GB_TILE_MODE10},
{GB_TILE_MODE11},
{GB_TILE_MODE12},
{GB_TILE_MODE13},
{GB_TILE_MODE14},
{GB_TILE_MODE15},
{GB_TILE_MODE16},
{GB_TILE_MODE17},
{GB_TILE_MODE18},
{GB_TILE_MODE19},
{GB_TILE_MODE20},
{GB_TILE_MODE21},
{GB_TILE_MODE22},
{GB_TILE_MODE23},
{GB_TILE_MODE24},
{GB_TILE_MODE25},
{GB_TILE_MODE26},
{GB_TILE_MODE27},
{GB_TILE_MODE28},
{GB_TILE_MODE29},
{GB_TILE_MODE30},
{GB_TILE_MODE31},
{mmGB_TILE_MODE0},
{mmGB_TILE_MODE1},
{mmGB_TILE_MODE2},
{mmGB_TILE_MODE3},
{mmGB_TILE_MODE4},
{mmGB_TILE_MODE5},
{mmGB_TILE_MODE6},
{mmGB_TILE_MODE7},
{mmGB_TILE_MODE8},
{mmGB_TILE_MODE9},
{mmGB_TILE_MODE10},
{mmGB_TILE_MODE11},
{mmGB_TILE_MODE12},
{mmGB_TILE_MODE13},
{mmGB_TILE_MODE14},
{mmGB_TILE_MODE15},
{mmGB_TILE_MODE16},
{mmGB_TILE_MODE17},
{mmGB_TILE_MODE18},
{mmGB_TILE_MODE19},
{mmGB_TILE_MODE20},
{mmGB_TILE_MODE21},
{mmGB_TILE_MODE22},
{mmGB_TILE_MODE23},
{mmGB_TILE_MODE24},
{mmGB_TILE_MODE25},
{mmGB_TILE_MODE26},
{mmGB_TILE_MODE27},
{mmGB_TILE_MODE28},
{mmGB_TILE_MODE29},
{mmGB_TILE_MODE30},
{mmGB_TILE_MODE31},
{CC_RB_BACKEND_DISABLE, true},
{GC_USER_RB_BACKEND_DISABLE, true},
{PA_SC_RASTER_CONFIG, true},
{mmGC_USER_RB_BACKEND_DISABLE, true},
{mmPA_SC_RASTER_CONFIG, true},
};
static uint32_t si_get_register_value(struct amdgpu_device *adev,
......
drivers/gpu/drm/amd/amdgpu/si_enums.h
View file @ 3e3fcd29
......@@ -121,15 +121,7 @@
#define CURSOR_UPDATE_LOCK (1 << 16)
#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
#define SI_CRTC0_REGISTER_OFFSET 0
#define SI_CRTC1_REGISTER_OFFSET 0x300
#define SI_CRTC2_REGISTER_OFFSET 0x2600
#define SI_CRTC3_REGISTER_OFFSET 0x2900
#define SI_CRTC4_REGISTER_OFFSET 0x2c00
#define SI_CRTC5_REGISTER_OFFSET 0x2f00
#define DMA0_REGISTER_OFFSET 0x000
#define DMA1_REGISTER_OFFSET 0x200
#define ES_AND_GS_AUTO 3
#define RADEON_PACKET_TYPE3 3
#define CE_PARTITION_BASE 3
......@@ -161,10 +153,6 @@
#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x02010002
#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
(((op) & 0xFF) << 8) | \
((n) & 0x3FFF) << 16)
......
drivers/gpu/drm/amd/amdgpu/sid.h
View file @ 3e3fcd29
......@@ -26,10 +26,6 @@
#define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
#define SI_MAX_SH_GPRS 256
#define SI_MAX_TEMP_GPRS 16
#define SI_MAX_SH_THREADS 256
......@@ -696,18 +692,6 @@
#define HDP_REG_COHERENCY_FLUSH_CNTL 0x1528
/* DCE6 ELD audio interface */
#define AZ_F0_CODEC_ENDPOINT_INDEX 0x1780
# define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0)
# define AZ_ENDPOINT_REG_WRITE_EN (1 << 8)
#define AZ_F0_CODEC_ENDPOINT_DATA 0x1781
#define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
#define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0)
#define SPEAKER_ALLOCATION_MASK (0x7f << 0)
#define SPEAKER_ALLOCATION_SHIFT 0
#define HDMI_CONNECTION (1 << 16)
#define DP_CONNECTION (1 << 17)
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */
......@@ -909,26 +893,11 @@
#define CRTC_STATUS_FRAME_COUNT 0x1BA6
/* Audio clocks */
#define DCCG_AUDIO_DTO_SOURCE 0x05ac
# define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
# define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */
#define DCCG_AUDIO_DTO0_PHASE 0x05b0
#define DCCG_AUDIO_DTO0_MODULE 0x05b4
#define DCCG_AUDIO_DTO1_PHASE 0x05c0
#define DCCG_AUDIO_DTO1_MODULE 0x05c4
#define AFMT_AUDIO_SRC_CONTROL 0x1c4f
#define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0)
/* AFMT_AUDIO_SRC_SELECT
* 0 = stream0
* 1 = stream1
* 2 = stream2
* 3 = stream3
* 4 = stream4
* 5 = stream5
*/
#define GRBM_CNTL 0x2000
#define GRBM_READ_TIMEOUT(x) ((x) << 0)
......@@ -977,30 +946,6 @@
#define SE_DB_BUSY (1 << 30)
#define SE_CB_BUSY (1 << 31)
#define GRBM_SOFT_RESET 0x2008
#define SOFT_RESET_CP (1 << 0)
#define SOFT_RESET_CB (1 << 1)
#define SOFT_RESET_RLC (1 << 2)
#define SOFT_RESET_DB (1 << 3)
#define SOFT_RESET_GDS (1 << 4)
#define SOFT_RESET_PA (1 << 5)
#define SOFT_RESET_SC (1 << 6)
#define SOFT_RESET_BCI (1 << 7)
#define SOFT_RESET_SPI (1 << 8)
#define SOFT_RESET_SX (1 << 10)
#define SOFT_RESET_TC (1 << 11)
#define SOFT_RESET_TA (1 << 12)
#define SOFT_RESET_VGT (1 << 14)
#define SOFT_RESET_IA (1 << 15)
#define GRBM_GFX_INDEX 0x200B
#define INSTANCE_INDEX(x) ((x) << 0)
#define SH_INDEX(x) ((x) << 8)
#define SE_INDEX(x) ((x) << 16)
#define SH_BROADCAST_WRITES (1 << 29)
#define INSTANCE_BROADCAST_WRITES (1 << 30)
#define SE_BROADCAST_WRITES (1 << 31)
#define GRBM_INT_CNTL 0x2018
# define RDERR_INT_ENABLE (1 << 0)
# define GUI_IDLE_INT_ENABLE (1 << 19)
......@@ -1045,16 +990,6 @@
#define VGT_VTX_VECT_EJECT_REG 0x222C
#define VGT_CACHE_INVALIDATION 0x2231
#define CACHE_INVALIDATION(x) ((x) << 0)
#define VC_ONLY 0
#define TC_ONLY 1
#define VC_AND_TC 2
#define AUTO_INVLD_EN(x) ((x) << 6)
#define NO_AUTO 0
#define ES_AUTO 1
#define GS_AUTO 2
#define ES_AND_GS_AUTO 3
#define VGT_ESGS_RING_SIZE 0x2232
#define VGT_GSVS_RING_SIZE 0x2233
......@@ -1072,11 +1007,6 @@
#define VGT_TF_MEMORY_BASE 0x226E
#define CC_GC_SHADER_ARRAY_CONFIG 0x226F
#define INACTIVE_CUS_MASK 0xFFFF0000
#define INACTIVE_CUS_SHIFT 16
#define GC_USER_SHADER_ARRAY_CONFIG 0x2270
#define PA_CL_ENHANCE 0x2285
#define CLIP_VTX_REORDER_ENA (1 << 0)
#define NUM_CLIP_SEQ(x) ((x) << 1)
......@@ -1169,89 +1099,6 @@
#define ROW_SIZE_MASK 0x30000000
#define ROW_SIZE_SHIFT 28
#define GB_TILE_MODE0 0x2644
# define MICRO_TILE_MODE(x) ((x) << 0)
# define ADDR_SURF_DISPLAY_MICRO_TILING 0
# define ADDR_SURF_THIN_MICRO_TILING 1
# define ADDR_SURF_DEPTH_MICRO_TILING 2
# define ARRAY_MODE(x) ((x) << 2)
# define ARRAY_LINEAR_GENERAL 0
# define ARRAY_LINEAR_ALIGNED 1
# define ARRAY_1D_TILED_THIN1 2
# define ARRAY_2D_TILED_THIN1 4
# define PIPE_CONFIG(x) ((x) << 6)
# define ADDR_SURF_P2 0
# define ADDR_SURF_P4_8x16 4
# define ADDR_SURF_P4_16x16 5
# define ADDR_SURF_P4_16x32 6
# define ADDR_SURF_P4_32x32 7
# define ADDR_SURF_P8_16x16_8x16 8
# define ADDR_SURF_P8_16x32_8x16 9
# define ADDR_SURF_P8_32x32_8x16 10
# define ADDR_SURF_P8_16x32_16x16 11
# define ADDR_SURF_P8_32x32_16x16 12
# define ADDR_SURF_P8_32x32_16x32 13
# define ADDR_SURF_P8_32x64_32x32 14
# define TILE_SPLIT(x) ((x) << 11)
# define ADDR_SURF_TILE_SPLIT_64B 0
# define ADDR_SURF_TILE_SPLIT_128B 1
# define ADDR_SURF_TILE_SPLIT_256B 2
# define ADDR_SURF_TILE_SPLIT_512B 3
# define ADDR_SURF_TILE_SPLIT_1KB 4
# define ADDR_SURF_TILE_SPLIT_2KB 5
# define ADDR_SURF_TILE_SPLIT_4KB 6
# define BANK_WIDTH(x) ((x) << 14)
# define ADDR_SURF_BANK_WIDTH_1 0
# define ADDR_SURF_BANK_WIDTH_2 1
# define ADDR_SURF_BANK_WIDTH_4 2
# define ADDR_SURF_BANK_WIDTH_8 3
# define BANK_HEIGHT(x) ((x) << 16)
# define ADDR_SURF_BANK_HEIGHT_1 0
# define ADDR_SURF_BANK_HEIGHT_2 1
# define ADDR_SURF_BANK_HEIGHT_4 2
# define ADDR_SURF_BANK_HEIGHT_8 3
# define MACRO_TILE_ASPECT(x) ((x) << 18)
# define ADDR_SURF_MACRO_ASPECT_1 0
# define ADDR_SURF_MACRO_ASPECT_2 1
# define ADDR_SURF_MACRO_ASPECT_4 2
# define ADDR_SURF_MACRO_ASPECT_8 3
# define NUM_BANKS(x) ((x) << 20)
# define ADDR_SURF_2_BANK 0
# define ADDR_SURF_4_BANK 1
# define ADDR_SURF_8_BANK 2
# define ADDR_SURF_16_BANK 3
#define GB_TILE_MODE1 0x2645
#define GB_TILE_MODE2 0x2646
#define GB_TILE_MODE3 0x2647
#define GB_TILE_MODE4 0x2648
#define GB_TILE_MODE5 0x2649
#define GB_TILE_MODE6 0x264a
#define GB_TILE_MODE7 0x264b
#define GB_TILE_MODE8 0x264c
#define GB_TILE_MODE9 0x264d
#define GB_TILE_MODE10 0x264e
#define GB_TILE_MODE11 0x264f
#define GB_TILE_MODE12 0x2650
#define GB_TILE_MODE13 0x2651
#define GB_TILE_MODE14 0x2652
#define GB_TILE_MODE15 0x2653
#define GB_TILE_MODE16 0x2654
#define GB_TILE_MODE17 0x2655
#define GB_TILE_MODE18 0x2656
#define GB_TILE_MODE19 0x2657
#define GB_TILE_MODE20 0x2658
#define GB_TILE_MODE21 0x2659
#define GB_TILE_MODE22 0x265a
#define GB_TILE_MODE23 0x265b
#define GB_TILE_MODE24 0x265c
#define GB_TILE_MODE25 0x265d
#define GB_TILE_MODE26 0x265e
#define GB_TILE_MODE27 0x265f
#define GB_TILE_MODE28 0x2660
#define GB_TILE_MODE29 0x2661
#define GB_TILE_MODE30 0x2662
#define GB_TILE_MODE31 0x2663
#define CB_PERFCOUNTER0_SELECT0 0x2688
#define CB_PERFCOUNTER0_SELECT1 0x2689
#define CB_PERFCOUNTER1_SELECT0 0x268A
......@@ -1263,10 +1110,6 @@
#define CB_CGTT_SCLK_CTRL 0x2698
#define GC_USER_RB_BACKEND_DISABLE 0x26DF
#define BACKEND_DISABLE_MASK 0x00FF0000
#define BACKEND_DISABLE_SHIFT 16
#define TCP_CHAN_STEER_LO 0x2B03
#define TCP_CHAN_STEER_HI 0x2B94
......@@ -1320,101 +1163,12 @@
# define CP_RINGID1_INT_STAT (1 << 30)
# define CP_RINGID0_INT_STAT (1 << 31)
#define CP_MEM_SLP_CNTL 0x3079
# define CP_MEM_LS_EN (1 << 0)
#define CP_DEBUG 0x307F
#define RLC_CNTL 0x30C0
# define RLC_ENABLE (1 << 0)
#define RLC_RL_BASE 0x30C1
#define RLC_RL_SIZE 0x30C2
#define RLC_LB_CNTL 0x30C3
# define LOAD_BALANCE_ENABLE (1 << 0)
#define RLC_SAVE_AND_RESTORE_BASE 0x30C4
#define RLC_LB_CNTR_MAX 0x30C5
#define RLC_LB_CNTR_INIT 0x30C6
#define RLC_CLEAR_STATE_RESTORE_BASE 0x30C8
#define RLC_UCODE_ADDR 0x30CB
#define RLC_UCODE_DATA 0x30CC
#define RLC_GPU_CLOCK_COUNT_LSB 0x30CE
#define RLC_GPU_CLOCK_COUNT_MSB 0x30CF
#define RLC_CAPTURE_GPU_CLOCK_COUNT 0x30D0
#define RLC_MC_CNTL 0x30D1
#define RLC_UCODE_CNTL 0x30D2
#define RLC_STAT 0x30D3
# define RLC_BUSY_STATUS (1 << 0)
# define GFX_POWER_STATUS (1 << 1)
# define GFX_CLOCK_STATUS (1 << 2)
# define GFX_LS_STATUS (1 << 3)
#define RLC_PG_CNTL 0x30D7
# define GFX_PG_ENABLE (1 << 0)
# define GFX_PG_SRC (1 << 1)
#define RLC_CGTT_MGCG_OVERRIDE 0x3100
#define RLC_CGCG_CGLS_CTRL 0x3101
# define CGCG_EN (1 << 0)
# define CGLS_EN (1 << 1)
#define RLC_TTOP_D 0x3105
# define RLC_PUD(x) ((x) << 0)
# define RLC_PUD_MASK (0xff << 0)
# define RLC_PDD(x) ((x) << 8)
# define RLC_PDD_MASK (0xff << 8)
# define RLC_TTPD(x) ((x) << 16)
# define RLC_TTPD_MASK (0xff << 16)
# define RLC_MSD(x) ((x) << 24)
# define RLC_MSD_MASK (0xff << 24)
#define RLC_LB_INIT_CU_MASK 0x3107
#define RLC_PG_AO_CU_MASK 0x310B
#define RLC_MAX_PG_CU 0x310C
# define MAX_PU_CU(x) ((x) << 0)
# define MAX_PU_CU_MASK (0xff << 0)
#define RLC_AUTO_PG_CTRL 0x310C
# define AUTO_PG_EN (1 << 0)
# define GRBM_REG_SGIT(x) ((x) << 3)
# define GRBM_REG_SGIT_MASK (0xffff << 3)
# define PG_AFTER_GRBM_REG_ST(x) ((x) << 19)
# define PG_AFTER_GRBM_REG_ST_MASK (0x1fff << 19)
#define RLC_SERDES_WR_MASTER_MASK_0 0x3115
#define RLC_SERDES_WR_MASTER_MASK_1 0x3116
#define RLC_SERDES_WR_CTRL 0x3117
#define RLC_SERDES_MASTER_BUSY_0 0x3119
#define RLC_SERDES_MASTER_BUSY_1 0x311A
#define RLC_GCPM_GENERAL_3 0x311E
#define DB_RENDER_CONTROL 0xA000
#define DB_DEPTH_INFO 0xA00F
#define PA_SC_RASTER_CONFIG 0xA0D4
# define RB_MAP_PKR0(x) ((x) << 0)
# define RB_MAP_PKR0_MASK (0x3 << 0)
# define RB_MAP_PKR1(x) ((x) << 2)
# define RB_MAP_PKR1_MASK (0x3 << 2)
# define RASTER_CONFIG_RB_MAP_0 0
# define RASTER_CONFIG_RB_MAP_1 1
# define RASTER_CONFIG_RB_MAP_2 2
# define RASTER_CONFIG_RB_MAP_3 3
// #define PA_SC_RASTER_CONFIG 0xA0D4
# define RB_XSEL2(x) ((x) << 4)
# define RB_XSEL2_MASK (0x3 << 4)
# define RB_XSEL (1 << 6)
# define RB_YSEL (1 << 7)
# define PKR_MAP(x) ((x) << 8)
# define PKR_MAP_MASK (0x3 << 8)
# define RASTER_CONFIG_PKR_MAP_0 0
# define RASTER_CONFIG_PKR_MAP_1 1
# define RASTER_CONFIG_PKR_MAP_2 2
# define RASTER_CONFIG_PKR_MAP_3 3
# define PKR_XSEL(x) ((x) << 10)
# define PKR_XSEL_MASK (0x3 << 10)
# define PKR_YSEL(x) ((x) << 12)
......@@ -1426,56 +1180,11 @@
# define SC_YSEL(x) ((x) << 20)
# define SC_YSEL_MASK (0x3 << 20)
# define SE_MAP(x) ((x) << 24)
# define SE_MAP_MASK (0x3 << 24)
# define RASTER_CONFIG_SE_MAP_0 0
# define RASTER_CONFIG_SE_MAP_1 1
# define RASTER_CONFIG_SE_MAP_2 2
# define RASTER_CONFIG_SE_MAP_3 3
# define SE_XSEL(x) ((x) << 26)
# define SE_XSEL_MASK (0x3 << 26)
# define SE_YSEL(x) ((x) << 28)
# define SE_YSEL_MASK (0x3 << 28)
#define VGT_EVENT_INITIATOR 0xA2A4
# define SAMPLE_STREAMOUTSTATS1 (1 << 0)
# define SAMPLE_STREAMOUTSTATS2 (2 << 0)
# define SAMPLE_STREAMOUTSTATS3 (3 << 0)
# define CACHE_FLUSH_TS (4 << 0)
# define CACHE_FLUSH (6 << 0)
# define CS_PARTIAL_FLUSH (7 << 0)
# define VGT_STREAMOUT_RESET (10 << 0)
# define END_OF_PIPE_INCR_DE (11 << 0)
# define END_OF_PIPE_IB_END (12 << 0)
# define RST_PIX_CNT (13 << 0)
# define VS_PARTIAL_FLUSH (15 << 0)
# define PS_PARTIAL_FLUSH (16 << 0)
# define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
# define ZPASS_DONE (21 << 0)
# define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
# define PERFCOUNTER_START (23 << 0)
# define PERFCOUNTER_STOP (24 << 0)
# define PIPELINESTAT_START (25 << 0)
# define PIPELINESTAT_STOP (26 << 0)
# define PERFCOUNTER_SAMPLE (27 << 0)
# define SAMPLE_PIPELINESTAT (30 << 0)
# define SAMPLE_STREAMOUTSTATS (32 << 0)
# define RESET_VTX_CNT (33 << 0)
# define VGT_FLUSH (36 << 0)
# define BOTTOM_OF_PIPE_TS (40 << 0)
# define DB_CACHE_FLUSH_AND_INV (42 << 0)
# define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
# define FLUSH_AND_INV_DB_META (44 << 0)
# define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
# define FLUSH_AND_INV_CB_META (46 << 0)
# define CS_DONE (47 << 0)
# define PS_DONE (48 << 0)
# define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
# define THREAD_TRACE_START (51 << 0)
# define THREAD_TRACE_STOP (52 << 0)
# define THREAD_TRACE_FLUSH (54 << 0)
# define THREAD_TRACE_FINISH (55 << 0)
/* PIF PHY0 registers idx/data 0x8/0xc */
#define PB0_PIF_CNTL 0x10
# define LS2_EXIT_TIME(x) ((x) << 17)
......@@ -1991,12 +1700,29 @@
//#dce stupp
/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
#define SI_CRTC0_REGISTER_OFFSET 0 //(0x6df0 - 0x6df0)/4
#define SI_CRTC1_REGISTER_OFFSET 0x300 //(0x79f0 - 0x6df0)/4
#define SI_CRTC2_REGISTER_OFFSET 0x2600 //(0x105f0 - 0x6df0)/4
#define SI_CRTC3_REGISTER_OFFSET 0x2900 //(0x111f0 - 0x6df0)/4
#define SI_CRTC4_REGISTER_OFFSET 0x2c00 //(0x11df0 - 0x6df0)/4
#define SI_CRTC5_REGISTER_OFFSET 0x2f00 //(0x129f0 - 0x6df0)/4
#define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) //(0x6df0 - 0x6df0)/4
#define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) //(0x79f0 - 0x6df0)/4
#define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) //(0x105f0 - 0x6df0)/4
#define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) //(0x111f0 - 0x6df0)/4
#define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) //(0x11df0 - 0x6df0)/4
#define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) //(0x129f0 - 0x6df0)/4
/* hpd instance offsets */
#define HPD0_REGISTER_OFFSET (0x1807 - 0x1807)
#define HPD1_REGISTER_OFFSET (0x180a - 0x1807)
#define HPD2_REGISTER_OFFSET (0x180d - 0x1807)
#define HPD3_REGISTER_OFFSET (0x1810 - 0x1807)
#define HPD4_REGISTER_OFFSET (0x1813 - 0x1807)
#define HPD5_REGISTER_OFFSET (0x1816 - 0x1807)
/* audio endpt instance offsets */
#define AUD0_REGISTER_OFFSET (0x1780 - 0x1780)
#define AUD1_REGISTER_OFFSET (0x1786 - 0x1780)
#define AUD2_REGISTER_OFFSET (0x178c - 0x1780)
#define AUD3_REGISTER_OFFSET (0x1792 - 0x1780)
#define AUD4_REGISTER_OFFSET (0x1798 - 0x1780)
#define AUD5_REGISTER_OFFSET (0x179d - 0x1780)
#define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780)
#define CURSOR_WIDTH 64
#define CURSOR_HEIGHT 64
......@@ -2036,9 +1762,6 @@
#define EVERGREEN_DATA_FORMAT 0x1ac0
# define EVERGREEN_INTERLEAVE_EN (1 << 0)
#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
#define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20)
#define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20)
#define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20)
......@@ -2050,32 +1773,6 @@
#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1847
#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a47
#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8
#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8
#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8
#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8
#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8
#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8
#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4
#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4
#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4
#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4
#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4
#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4
#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000
#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000
#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000
#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000
#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000
#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000
#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x1
#define R600_D1GRPH_SWAP_CONTROL 0x1843
#define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
#define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
......@@ -2099,8 +1796,6 @@
# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
#define FMT_BIT_DEPTH_CONTROL 0x1bf2
#define FMT_TRUNCATE_EN (1 << 0)
#define FMT_TRUNCATE_DEPTH (1 << 4)
......@@ -2404,19 +2099,6 @@
#define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC_MASK 0x800
#define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC__SHIFT 0xb
#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
#define MC_SEQ_MISC0__MT__MASK 0xf0000000
#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
#define MC_SEQ_MISC0__MT__DDR2 0x20000000
......@@ -2426,10 +2108,7 @@
#define MC_SEQ_MISC0__MT__HBM 0x60000000
#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
#define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
#define PACKET3_SEM_SEL_WAIT (0x7 << 29)
......
drivers/gpu/drm/amd/amdkfd/kfd_debug.c
View file @ 3e3fcd29
......@@ -357,12 +357,12 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en)
return 0;
if (!pdd->proc_ctx_cpu_ptr) {
r = amdgpu_amdkfd_alloc_gtt_mem(adev,
AMDGPU_MES_PROC_CTX_SIZE,
&pdd->proc_ctx_bo,
&pdd->proc_ctx_gpu_addr,
&pdd->proc_ctx_cpu_ptr,
false);
r = amdgpu_amdkfd_alloc_gtt_mem(adev,
AMDGPU_MES_PROC_CTX_SIZE,
&pdd->proc_ctx_bo,
&pdd->proc_ctx_gpu_addr,
&pdd->proc_ctx_cpu_ptr,
false);
if (r) {
dev_err(adev->dev,
"failed to allocate process context bo\n");
......
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
View file @ 3e3fcd29
......@@ -1221,11 +1221,13 @@ static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
decrement_queue_count(dqm, qpd, q);
if (dqm->dev->kfd->shared_resources.enable_mes) {
retval = remove_queue_mes(dqm, q, qpd);
if (retval) {
int err;
err = remove_queue_mes(dqm, q, qpd);
if (err) {
dev_err(dev, "Failed to evict queue %d\n",
q->properties.queue_id);
goto out;
retval = err;
}
}
}
......