- Feb 01, 2023
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Alex Deucher authored
Causes flickering or white screens in some configurations. Disable it for now until we can fix the issue. Bug: drm/amd#2352 Cc: roman.li@amd.com Cc: yifan1.zhang@amd.com Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Causes flickering or white screens in some configurations. Disable it for now until we can fix the issue. Bug: drm/amd#2352 Cc: roman.li@amd.com Cc: yifan1.zhang@amd.com Reviewed-by:
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Yifan Zha authored
[Why] Accessing GRBM_GFX_CNTL in full access time has risk when VF is doing MMIO attacking. Therefore, VF writing GRBM_GFX_CNTL are blocked by L1 Policy. For RLCG interface, RLCG use SCRATCH_REG2 which is copied from GRBM_GFX_CNTL. [How] Remove writing GRBM_GFX_CNTL in amdgpu_virt_rlcg_reg_rw. v2: Remove directly writing GRBM_GFX_INDEX in amdgpu_virt_rlcg_reg_rw as RLCG interface no need to use it. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com>
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- Jan 31, 2023
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Vitaly Prosyak authoredWe allow sending PSP messages LOAD_ASD and UNLOAD_TA without acquiring a lock in drm_dev_enter during driver unload because we must call drm_dev_unplug as the beginning of unload driver sequence. Added WARNING if other PSP messages are sent without a lock. After this commit, the following commands would work -sudo modprobe -r amdgpu -sudo modprobe amdgpu Signed-off-by:Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by Alex Deucher <alexander.deucher@amd.com> Change-Id: I57f65fe820e2f7055f8065cd18c63fe6ff3ab694
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Guilherme G. Piccoli authoredThis is a very trivial code clean-up related to commit 5468c36d ("drm/amd/display: Filter Invalid 420 Modes for HDMI TMDS"). This commit added a validation on driver probe to prevent invalid TMDS modes, but one of the fake properties (swizzle) ended-up causing a warning on driver probe; was reported here: drm/amd#2264 . It was fixed by commit 105a8b86 ("drm/amd/display: patch cases with unknown plane state to prevent warning"), but the validation code had a double variable assignment, which we hereby remove. Also, the fix relies in the dcn2{0,1}patch_unknown_plane_state() callbacks, so while at it we took the opportunity to perform a small code clean-up in such routines. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Daniel Wheeler <daniel.wheeler@amd.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Mark Broadworth <mark.broadworth@amd.com> Cc: Melissa Wen <mwen@igalia.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Sung Joon Kim <Sungjoon.Kim@amd.com> Cc: Swapnil Patel <Swapnil.Patel@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by:
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Tom Rix authored
cppcheck reports drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c:1403:76: style: Expression is always true because 'else if' condition is opposite to previous condition at line 1396. [multiCondition] } else if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { ^ drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c:1396:69: note: first condition if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type != SUBVP_PHANTOM) { ^ drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c:1403:76: note: else if condition is opposite to first condition } else if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { It is not necessary to explicitly the check != condition, an else is simplier. Fixes: 238debca ("drm/amd/display: Use DML for MALL SS and Subvp allocation calculations") Signed-off-by:Tom Rix <trix@redhat.com> Signed-off-by:
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Tom Rix authored
checkpatch reports drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:2902:13: style: Expression is always true because 'else if' condition is opposite to previous condition at line 2895. [multiCondition] } else if (blank) { ^ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:2895:6: note: first condition if (!blank) { ^ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:2902:13: note: else if condition is opposite to first condition } else if (blank) { It is not necessary to explicitly the check != condition, an else is simplier. Fixes: aa5a5777 ("drm/amd/display: Vari-bright looks disabled near end of MM14") Signed-off-by: -
ye xingchen authored
opp.h is included more than once. Signed-off-by:
ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by:
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Jonathan Neuschäfer authored
Spell it as "broadcast". Signed-off-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by:
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Alex Deucher authored
There could be boards with DCN listed in IP discovery, but no display hardware actually wired up. In this case the vbios display table will not be populated. Detect this case and skip loading DM when we detect it. v2: Mark DCN as harvested as well so other display checks elsewhere in the driver are handled properly. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Yiqing Yao authored
These sysfs nodes are tested supported, so enable them. Signed-off-by:
Yiqing Yao <yiqing.yao@amd.com> Reviewed-by:
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- Jan 30, 2023
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Mario Limonciello authored
A mistake has been made on some boards with NBIO 4.3.0 where some NBIO registers aren't properly set by the hardware. Ensure that they're set during initialization. Cc: Natikar Basavaraj <Basavaraj.Natikar@amd.com> Tested-by:
Satyanarayana ReddyTVN <Satyanarayana.ReddyTVN@amd.com> Tested-by:
Rutvij Gajjar <Rutvij.Gajjar@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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Evan Quan authored
Enable HDP clock gating control for gfx 11.0.3. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Change-Id: I0bac85a05692937917e2916e79e6e74a1e11aec0
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Tim Huang authored
PMFW will handle the features disablement properly for gpu reset case, driver involvement may cause some unexpected issues. Cc: stable@vger.kernel.org #6.1 Signed-off-by:
Tim Huang <tim.huang@amd.com> Reviewed-by:
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- Jan 27, 2023
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This version brings along following fixes: - fix linux dp link lost handled only one time - Reset DMUB mailbox SW state after HW reset - Unassign does_plane_fit_in_mall function from dcn3.2 - Add Function delaration in dc_link - Fix crash when connecting 2 displays with video playback - Adjust downscaling limits for dcn314 - fix FCLK pstate change underflow - Fix only one ABM pipe enabled under ODM combined case - Add missing brackets in calculation - Correct bw_params population - Fix Z8 support configurations - Add Debug Log for MST and PCON - fix MALL size hardcoded for DCN321 - add rc_params_override option in dc_dsc_config - Enable Freesync over PCon Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com>
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[Why] linux amdgpu defer handle link lost irq. dm add handle request to irq work queue for the first irq of link lost. if link training fails for link lost handle, link will not be enabled anymore. [How] allow adding handle request of link lost to work queue before running dp link training for link lost. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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[Why] Otherwise we can be out of sync with what's in the hardware, leading to us rerunning every command that's presently in the ringbuffer. [How] Reset software state for the mailboxes in hw_reset callback. This is already done as part of the mailbox init in hw_init, but we do need to remember to reset the last cached wptr value as well here. Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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[Why] The hwss function does_plane_fit_in_mall not applicable to dcn3.2 asics. Using it with dcn3.2 can result in undefined behaviour. [How] Assign the function pointer to NULL. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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[WHY] Housekeeping cleaning and adding declaration for function to be called from DM layer [HOW] Adding public functions to dc_link.h Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Mustapha Ghaddar <mghaddar@amd.com> Tested-by:
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This reverts commit 82dca857. Acked-by:
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[Why] Lower max_downscale_ratio and ARGB888 downscale factor to prevent cases where underflow may occur on dcn314 [How] Set max_downscale_ratio to 400 and ARGB downscale factor to 250 for dcn314 Reviewed-by:
Daniel Miess <Daniel.Miess@amd.com> Tested-by:
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[Why] Currently we set FCLK p-state change watermark calculated based on dummy p-state latency when UCLK p-state is not supported [How] Calculate FCLK p-state change watermark based on on FCLK pstate change latency in case UCLK p-state is not supported Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
Vladimir Stempen <vladimir.stempen@amd.com> Tested-by:
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[Why] ABM set pipe before updating ODM status, it leads to incorrect ABM pipe setting when enabling ODM combine. [How] Call ABM set pipe flow after ODM status update in program pipe sequence. Reviewed-by:
Chun-Liang Chang <Chun-Liang.Chang@amd.com> Reviewed-by:
Leon Huang <Leon.Huang1@amd.com> Tested-by:
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[Why] Brackets missing in the calculation for MIN_DST_Y_NEXT_START [How] Add missing brackets for this calculation Reviewed-by:
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[Why] Underflow observed during P010 video playback on dcn314 due to incorrectly populated bw_params [How] Populate fclk, memclk and voltage in bw_params with values from max pstate rather than min pstate Reviewed-by:
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[Why] It's not supported in multi-display, but it is supported in 2nd eDP screen only. [How] Remove multi display support, restrict number of planes for all z-states support, but still allow Z8 if we're not using PWRSEQ0. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Add log for MST/PCON specific use case: 1. If DP1.2 hub where gives reduced link bw and no dsc support. 2. If less than 4-lane configuration where gives reduced bw. 3. If FRL PCON enabled for asic. 4. Track MST sink count. Reviewed-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by:
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[Why] MALL size available can vary for different SKUs MALL size was still hardcoded for DCN321 [How] Remove hardcoding MALL size for DCN321 Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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[why] Current RC params are based on VESA recommended configurations. Some DSC sink may prefer non standard rc params values due to hardware limitations. To support those DSC sink we will allow DM to optionally pass rc_params_ovrd in dc_dsc_config so DC will override the default VESA recommended configurations. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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[why] Enable Freesync over PCon on Linux environment. [how] Adding Freesync over PCon support in amdgpu_dm - Read DPCD for Freesync over PCon capabilitiy - Add whitelist for compatible branch devices Reviewed-by:
Chao-kai Wang <Stylon.Wang@amd.com> Acked-by:
Sung Joon Kim <sungkim@amd.com> Tested-by:
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- Jan 26, 2023
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The newly added code is in an #ifdef, so the variables that are only used in there cause a warning if CONFIG_DRM_AMD_DC_DCN is disabled: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function 'amdgpu_dm_atomic_check': drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:9698:43: error: unused variable 'mst_state' [-Werror=unused-variable] 9698 | struct drm_dp_mst_topology_state *mst_state; | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:9697:41: error: unused variable 'mgr' [-Werror=unused-variable] 9697 | struct drm_dp_mst_topology_mgr *mgr; | ^~~ Fixes: c689e1e3 ("drm/amdgpu/display/mst: Fix mst_state->pbn_div and slot count assignments") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com>
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- Jan 25, 2023
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Graham Sider authored
SQ_WAVE_INST_DW0 isn't present on gfx11 compared to gfx10, so update wave data type to signify a difference. Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
Mukul Joshi <Mukul.Joshi@amd.com>
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Mario Limonciello authored
We guard the suspend entry code from running unless we have proper BIOS support for either S3 mode or s0ix mode. If a user's system doesn't support either of these modes the kernel still does offer s2idle in `/sys/power/mem_sleep` so there is an expectation from users that it works even if the power consumption remains very high. Rafael Ávila de Espíndola reports that a system of his has a non-functional graphics stack after resuming. That system doesn't support S3 and the FADT doesn't indicate support for low power idle. Through some experimentation it was concluded that even without the hardware s0i3 support provided by the amd_pmc driver the power consumption over suspend is decreased by running amdgpu's s0ix suspend routine. The numbers over suspend showed: * No patch: 9.2W * Skip amdgpu suspend entirely: 10.5W * Run amdgpu s0ix routine: 7.7W As this does improve the power, remove some of the guard rails in `amdgpu_acpi.c` for only running s0ix suspend routines in the right circumstances. However if this turns out to cause regressions for anyone, we should revert this change and instead opt for skipping suspend/resume routines entirely or try to fix the underlying behavior that makes graphics fail after resume without underlying platform support. Reported-by:
Rafael Ávila de Espíndola <rafael@espindo.la> Link: drm/amd#2364 Acked-by:
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This reverts commit fac53471. The following change: move the drm_dev_unplug call after amdgpu_driver_unload_kms in amdgpu_pci_remove. The reason is the following: amdgpu_pci_remove calls drm_dev_unregister and it should be called first to ensure userspace can't access the device instance anymore. If we call drm_dev_unplug after amdgpu_driver_unload_kms then we observe IGT PCI software unplug test failure (kernel hung) for all ASICs. This is how this regression was found. After this revert, the following commands do work not, but it would be fixed in the next commit: - sudo modprobe -r amdgpu - sudo modprobe amdgpu Signed-off-by:
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- Jan 24, 2023
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Alex Deucher authored
VCN4.x supports AV1 encode. Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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- Jan 23, 2023
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This version brings along following fixes: - Fix timing not changning when freesync video is enabled - avoid disable otg when dig was disabled - Properly reuse completion structure - Pass DSC slice height to PSR FW - merge dc_link_dp into dc_link - move dp cts functions from dc_link_dp to link_dp_cts - move dp irq handler functions from dc_link_dp to link_dp_irq_handler - Enable AdaptiveSync in DC interface - adjust MALL size available for DCN32 and DCN321 - Set init freq for DCFCLK DS - Use |= when assigning wm_optimized_required - move eDP panel control logic to link_edp_panel_control - create accessories, hwss and protocols sub folders in link - Disable SubVP for PSR panels Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
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[Why&How] Switching between certain modes that are freesync video modes and those are not freesync video modes result in timing not changing as seen by the monitor due to incorrect timing being driven. The issue is fixed by ensuring that when a non freesync video mode is set, we reset the freesync status on the crtc. Reviewed-by:
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[Why] This is a workaround for an dcn3.1 hang that happens if otg dispclk is ramped while otg is on and stream enc is off. But this w/a should not trigger when we have a dig active. [How] Avoid disable otg when dig was disabled. Reviewed-by:
Jingwen Zhu <Jingwen.Zhu@amd.com> Tested-by:
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[Why] Connecting displays to TBT3 docks often produces invalid replies for DPIA AUX requests. It turns out the completion structure was not re-initialized before reusing it, resulting in immature wake up to completion. [How] Properly call reinit_completion() on reused completion structure. Cc: stable@vger.kernel.org Reviewed-by:
Solomon Chiu <solomon.chiu@amd.com> Acked-by:
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[Why] When DSC is enabled, the PSRSU seletive update region must be multiple number of DSC slice height number. The original solution is to overwrite the SU Y granularity by DSC slice height in DAL driver. However, the size of the SU Y granularity variable only has 8 bytes and the DSC slice height may over the 8 bytes size. [How] Instead of overwriting the SU Y granularity value, add a new DSC slice height pararmeter and pass it to DMUB PSRSU FW. The PSRSU FW will refer to the DSC slice height value and extend the SU region. Reviewed-by:
Dennis Chan <dennis.chan@amd.com> Reviewed-by:
ChunTao Tso <chuntao.tso@amd.com> Acked-by:
Robin Chen <robin.chen@amd.com> Tested-by:
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