- Feb 23, 2025
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[why] some board designs have eDP0 connected to DP1, need a way to enable support_edp0_on_dp1 flag, otherwise edp related features cannot work [how] do a dmi check during dm initialization to identify systems that require support_edp0_on_dp1. Optimize quirk table with callback functions to set quirk entries, retrieve_dmi_info can set quirks according to quirk entries Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Yilin Chen <Yilin.Chen@amd.com> Signed-off-by:
Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com>
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[WHY] replace dio encoder access to work with new dio encoder assignment. [HOW} 1. before validation, access dio encoder by get_temp_dio_link_enc() 2. after validation, access dio encoder through pipe_ctx->link_res Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by:
Peichen Huang <PeiChen.Huang@amd.com> Signed-off-by:
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[Why] In order to avoid component conflicts, spl namespace is needed. [How] Adding SPL namespace to the public API os that each user of SPL can have their own namespace. Signed-off-by:
Navid Assadian <Navid.Assadian@amd.com> Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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[Why] Some of unit tests use large scaling ratio such that when we calculate optimal number of taps, max_taps is negative. Then in recent change, we changed max_taps to uint instead of int so now max_taps wraps and is positive. This change changed the behaviour from returning back false to return true and breaks unit test check [How] Add check to prevent max_taps from wrapping and set to 0 instead Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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[Why] IDENTITY_RATIO check uses 2 bits for integer, which only allows checking downscale ratios up to 3. But we support up to 6x downscale [How] Update IDENTITY_RATIO to check 3 bits for integer Add ASSERT to catch if we downscale more than 6x Signed-off-by:
Jun Lei <jun.lei@amd.com> Tested-by:
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The mismatch type comparison/assignment may cause data loss. Since the values are always non-negative, it is safe to use unsigned variables to resolve the mismatch. Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Tested-by:
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[Why] For subsampled YUV output formats, more pixels can get fetched and be used for scaling. [How] Add the adjustment to the calculated recout, so the viewport covers the corresponding pixels on the source plane. Signed-off-by:
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[Why & How] Passing uint into uchar function param. Pass uint instead Signed-off-by:
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[Why] DCN36 should inherit the same policy as DCN35 for DML2. [How] Add it to the list of checks in translation helper. Signed-off-by:
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[WHAT & HOW] Fix the incorrect value of the cursor_buffer_size. Signed-off-by:
Alex Hung <alex.hung@amd.com> Reviewed-by:
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[Why] PSR-SU may cause some glitching randomly on several panels. [How] Temporarily disable the PSR-SU and fallback to PSR1 for all eDP panels. Link: drm/amd#3388 Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Sun peng Li <sunpeng.li@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Roman Li <roman.li@amd.com> Tested-by:
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This reverts commit 9b908d78. We planning to disable the PSR-SU and fallback to PSR1 for all eDP panels not only for specific eDP panel temporarily. Reviewed-by:
Sun peng Li <sunpeng.li@amd.com>
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- Feb 21, 2025
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Colin Ian King authored
There is a spelling mistake in max_oustanding_when_urgent_expected, fix it. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Aurabindo Pillai authored
Chaitanya is no longer with AMD, and the responsibility has been taken over by Austin. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com>
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Melissa Wen authoredWhen switching to drm_edid, we slightly changed how to get edid by removing the possibility of getting them from dc_link when in aux transaction mode. As MST doesn't initialize the connector with `drm_connector_init_with_ddc()`, restore the original behavior to avoid functional changes. v2: - Fix build warning of unchecked dereference (kernel test bot) CC: Alex Hung <alex.hung@amd.com> CC: Mario Limonciello <mario.limonciello@amd.com> CC: Roman Li <Roman.Li@amd.com> CC: Aurabindo Pillai <Aurabindo.Pillai@amd.com> Fixes: 48edb2a4 ("drm/amd/display: switch amdgpu_dm_connector to use struct drm_edid") Reviewed-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Dr. David Alan Gilbert authored
The nbif_v6_3_1_sriov_funcs instance of amdgpu_nbio_funcs was added in commit 894c6d35 ("drm/amdgpu: Add nbif v6_3_1 ip block support") but has remained unused. Alex has confirmed it wasn't needed. Remove it, together with the four unused stub functions: nbif_v6_3_1_sriov_ih_doorbell_range nbif_v6_3_1_sriov_gc_doorbell_init nbif_v6_3_1_sriov_vcn_doorbell_range nbif_v6_3_1_sriov_sdma_doorbell_range Signed-off-by:
Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by:
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Rodrigo Siqueira authoredMap all of my previously used email addresses to my @igalia.com address. Acked-by:
Rodrigo Siqueira <siqueira@igalia.com> Signed-off-by:
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Sathishkumar S authored
Add ring reset function callback for JPEG5_0_1 to recover from job timeouts without a full gpu reset. Signed-off-by:
Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com>
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Rodrigo Siqueira authored
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André Almeida authoredWhen a ring reset happens, the kernel log shows only "amdgpu: Starting <ring name> ring reset", but when it finishes nothing appears in the log. Explicitly write in the log that the reset has finished correctly. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
André Almeida <andrealmeid@igalia.com> Signed-off-by:
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André Almeida authored
After a GPU reset happens, the driver creates a coredump file. However, the user might not be aware of it. Log the file creation the user can find more information about the device and add the file to bug reports. This is similar to what the xe driver does. Reviewed-by:
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Alex Deucher authored
Re-send the mes message on resume to make sure the mes state is up to date. Fixes: 8521e3c5 ("drm/amd/amdgpu: limit single process inside MES") Acked-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Signed-off-by:
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Asad Kamal authored
Use separate metrics table for smu_v13_0_12 and fetch metrics data using that. v2: Fix jpeg busy indexing (Lijo) Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com>
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Sathishkumar S authored
Add core reset control register definitions and align all prior register definitions to end at 100 column length for uniformity. Signed-off-by:
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Sathishkumar S authored
Add helper functions to handle per-instance and per-core initialization and deinitialization in JPEG5_0_1. Signed-off-by:
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Aurabindo Pillai authored
Remove extraneous tab and newline in dml2_core_dcn4.c that was reported by the bot Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202502211920.txUfwtSj-lkp@intel.com/ Fixes: 70839da6 ("drm/amd/display: Add new DCN401 sources") Signed-off-by:
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Alex Deucher authored
Xinhui's email is no longer valid. Reviewed-by:
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Alex Deucher authored
There was a quirk added to add a workaround for a Sapphire RX 5600 XT Pulse that didn't allow BAR resizing. However, the quirk caused a regression with runtime pm on Dell laptops using those chips, rather than narrowing the scope of the resizing quirk, add a quirk to prevent amdgpu from resizing the BAR on those Dell platforms unless runtime pm is disabled. v2: update commit message, add runpm check Closes: drm/amd#1707 Fixes: 907830b0 ("PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse") Reviewed-by:
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Asad Kamal authored
Fetch fru product info for smu_v13_0_12 from static metrics table v2: Field by field copy for fru info(Lijo) Signed-off-by:
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Asad Kamal authored
Fetch clock frequency table from static metrics table for smu_v13_0_12 v2: Move PPTable definition, remove unnecessary checks for getting static metrics table(Lijo) Signed-off-by:
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Asad Kamal authored
Add GetStaticMetricTable message for smu_v13_0_12 Signed-off-by:
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Asad Kamal authored
Update pmfw headers for smu_v13_0_12 new messages & metrics table. Static metrics table for frequency added, Separate metrics table for smu_v13_0_12 added. Signed-off-by:
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Jie1zhang authored
This reverts commit 2b784ba7503fbc731ebf26480b91ced76f9a6d12 Signed-off-by:
Jesse Zhang <jesse.zhang@amd.com> Reviewed-by:
Tim Huang <tim.huang@amd.com>
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Jie1zhang authored
This patch updates the `amdgpu_job_timedout` function to check if the ring is actually guilty of causing the timeout. If not, it skips error handling and fence completion. v2: move the is_guilty check down into the queue reset area (Alex) v3: need to call is_guilty before reset (Alex) Signed-off-by:
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- Introduce a new function `sdma_v4_4_2_init_sysfs_reset_mask` to initialize the sysfs reset mask for SDMA. - Move the initialization of the sysfs reset mask to the `late_init` stage to ensure that the SMU initialization and capability setup are completed before checking the SDMA reset capability. - Consolidate the logic for setting the supported reset types and initializing the sysfs reset mask into the new function. - For IP versions 9.4.3 and 9.4.4, enable per-queue reset if the MEC firmware version is at least 0xb0 and PMFW supports queue reset. - Add a TODO comment for future support of per-queue reset for IP version 9.4.5. This change ensures that per-queue reset is only enabled when the MEC and PMFW support it. Suggested-by:Jonathan Kim <Jonathan.Kim@amd.com> Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by:
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This patch introduces a new function to check if the SMU supports resetting the SDMA engine. This capability check ensures that the driver does not attempt to reset the SDMA engine on hardware that does not support it. The following changes are included: - New function `amdgpu_dpm_reset_sdma_is_supported` to check SDMA reset support at the AMDGPU driver level. - New function `smu_reset_sdma_is_supported` to check SDMA reset support at the SMU level. - Implementation of `smu_v13_0_6_reset_sdma_is_supported` for the specific SMU version v13.0.6. - Updated `smu_v13_0_6_reset_sdma` to use the new capability check before attempting to reset the SDMA engine. v2: change smu_reset_sdma_is_supported type to bool (Tim) Signed-off-by:
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This patch adds a reset function pointer to the SDMA v4.4.2 page ring functionality. The new function pointer `reset` is set to `sdma_v4_4_2_reset_queue`, which is responsible for resetting the SDMA queue. Changes: - Add `reset` function pointer to `sdma_v4_4_2_page_ring_funcs`. Signed-off-by:
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This patch includes the remaining improvements to the SDMA reset logic: - Added `gfx_guilty` and `page_guilty` flags to track guilty queues. - Updated the reset and resume functions to handle the guilty state. - Cached the `rptr` before reset. v2: 1.replace the caller with a guilty bool. If the queue is the guilty one, set the rptr and wptr to the saved wptr value, else, set the rptr and wptr to the saved rptr value. (Alex) 2. cache the rptr before the reset. (Alex) v3: Keeping intermediate variables like u64 rwptr simplifies resotre rptr/wptr.(Lijo) Suggested-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Signed-off-by:
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This patch introduces the `is_guilty` callbacks for the GFX and PAGE rings. These callbacks check if a ring is guilty of causing a timeout or error. Suggested-by:
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This patch introduces the following changes: - Add `cached_rptr` to the `amdgpu_ring` structure to store the read pointer before a reset. - Add `is_guilty` callback to the `amdgpu_ring_funcs` structure to check if a ring is guilty of causing a timeout. Suggested-by:
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