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- Sep 14, 2021
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Nirmoy Das authored
debugfs APIs returns encoded error so use IS_ERR for checking return value. v2: return PTR_ERR(ent) References: drm/amd#1686 Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-By:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Sep 07, 2021
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chongjiapeng authored
drm/amd/display: make configure_lttpr_mode_transparent and configure_lttpr_mode_non_transparent static This symbols is not used outside of dc_link_dp.c, so marks it static. Fix the following sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1766:16: warning: symbol 'configure_lttpr_mode_non_transparent' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1755:16: warning: symbol 'configure_lttpr_mode_transparent' was not declared. Should it be static? Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
chongjiapeng <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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chongjiapeng authored
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c:643:35-36: WARNING comparing pointer to 0. Reported-by:
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Colin Ian King authored
The variables hi_sidd and lo_sidd are being initialized with a values that are never read, they are being updated later on. The assignments are redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Simon Ser authored
In amdgpu_dm_atomic_check, dc_validate_global_state is called. On failure this logs a warning to the kernel journal. However warnings shouldn't be used for atomic test-only commit failures: user-space might be perfoming a lot of atomic test-only commits to find the best hardware configuration. Downgrade the log to a regular DRM atomic message. While at it, use the new device-aware logging infrastructure. This fixes error messages in the kernel when running gamescope [1]. [1]: https://github.com/Plagman/gamescope/issues/245 Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Simon Ser <contact@emersion.fr> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Len Baker authored
As noted in the "Deprecated Interfaces, Language Features, Attributes, and Conventions" documentation [1], size calculations (especially multiplication) should not be performed in memory allocator (or similar) function arguments due to the risk of them overflowing. This could lead to values wrapping around and a smaller allocation being made than the caller was expecting. Using those allocations could lead to linear overflows of heap memory and other misbehaviors. So, refactor the code a bit to use the purpose specific kcalloc() function instead of the calculated size argument in the kzalloc() function. [1] https://www.kernel.org/doc/html/v5.14/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments Signed-off-by:
Len Baker <len.baker@gmx.com> Signed-off-by:
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Colin Ian King authored
There is a statement that is indented incorrectly. Clean it up. Reviewed-by:
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Colin Ian King authored
There are a couple of statements that are indented one character too deeply, clean these up. Reviewed-by:
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Christian König authored
Just drop some dead code. Signed-off-by:
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Christian König authored
The memory backing old_mem is already freed at that point, move the check a bit more up. Signed-off-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Candice Li authored
Creat common PSP TA load function and update PSP ta_mem_context with size information. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Kenneth Feng authored
fix the issue of uploading powerplay table due to the dependancy of rlc. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Jack Gui <Jack.Gui@amd.com> Signed-off-by:
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- Sep 02, 2021
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Ernst Persson authored
Seems like newer cards can have even more instances now. Found by UBSAN: array-index-out-of-bounds in drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:318:29 index 8 is out of range for type 'uint32_t *[8]' Bug: drm/amd#1697 Cc: stable@vger.kernel.org Signed-off-by:
Ernst Sjöstrand <ernstp@gmail.com> Signed-off-by:
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- Sep 01, 2021
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Colin Ian King authored
Pointer sink is being inintialized with a value that is never read, it is later being re-assigned a new value. Remove the redundant initialization. Addresses-Coverity: ("Unused value") Signed-off-by: -
Yifan Zha authored
[Why] Sending invalid SMU message in sriov cause set dpm level fail. [How] Update message table based on SMU firmware. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Review-by:
Horace Chen <Horace.Chen@amd.com> Signed-off-by:
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Satyajit Sahu authored
Schedule the encode job in VCE/VCN encode ring based on the priority set by UMD. Signed-off-by:
Satyajit Sahu <satyajit.sahu@amd.com> Reviewed-by:
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Satyajit Sahu authored
VCN has multiple rings. Set the proper priority level for each encode ring while initializing. Signed-off-by:
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Satyajit Sahu authored
VCE has multiple rings. Set the proper priority level for each ring while initializing. Signed-off-by:
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Candice Li authored
Add MPIO to RAS block Signed-off-by:
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Candice Li authored
Create common PSP TA unload function and replace all common TA unloading sequences. Signed-off-by:
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Tom Denis authored
This new debugfs interface uses an IOCTL interface in order to pass along state information like SRBM and GRBM bank switching. This new interface also allows a full 32-bit MMIO address range which the previous didn't. With this new design we have room to grow the flexibility of the file as need be. (v2): Move read/write to .read/.write, fix style, add comment for IOCTL data structure (v3): C style comments (v4): use u32 in struct and remove offset variable (v5): Drop flag clearing in op function, use 0xFFFFFFFF for broadcast instead of 0x3FF, use mutex for op/ioctl. Signed-off-by:Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Colin Ian King authored
There is a spelling mistake in a DC_LOG_WARNING message. Fix it. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Nirmoy Das authored
Currently AMDGPU_RING_PRIO_MAX is redefinition of a max gfx hwip priority, this won't work well when we will have a hwip with different set of priorities than gfx. Also, HW ring priorities are different from ring priorities. Create a global enum for ring priority levels which each HWIP can use to define its own priority levels. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Nirmoy Das authored
To get a hardware queue priority for a context, we are currently mapping AMDGPU_CTX_PRIORITY_* to DRM_SCHED_PRIORITY_* and then to hardware queue priority, which is not the right way to do that as DRM_SCHED_PRIORITY_* is software scheduler's priority and it is independent from a hardware queue priority. Use userspace provided context priority, AMDGPU_CTX_PRIORITY_* to map a context to proper hardware queue priority. Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - FW promotion 0.0.80 - Add missing ABM register offsets - Fix in swizzle mode mapping - Emulated sink support for freesync - Improvoments in max target bpp Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <Daniel.Wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
- Add volatile to avoid incomplete flushing of data in rb Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Alvin Lee authored
[Why] Swizzle mode enum for DC_SW_VAR_R_X was existing, but not mapped correctly. [How] Update mapping and conversion for DC_SW_VAR_R_X. Reviewed-by:
XiangBing Foo <XiangBing.Foo@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Cc: stable@vger.kernel.org Tested-by:
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Wyatt Wood authored
[Why + How] Initialize GSP1 SDP header for use in DMCUB FW. Reviewed-by:
Wyatt Wood <wyatt.wood@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why] When forced modes are used during certain IGT tests, without a real connector, dc_sink would be null when standard modes are added by the driver. Calling the function to update freesync capabilities at this point will result in an error being printed [How] Use emulated sink when available. If both the normal and emulated sink are not available, set all freesync parameters to 0. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Roman Li authored
[Why] Some monitors exhibit corruption at 16bpp DSC. [How] - Add helpers for patching edid caps. - Use it for limiting DSC target bitrate to 15bpp for known monitors Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Roman Li <Roman.Li@amd.com> Cc: stable@vger.kernel.org Tested-by:
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Roman Li authored
[Why] Max target bpp override is an option for working around DSC issues. It is supported on DC level, but was not used in DM. [How] Use actual option value instead of 0. Reviewed-by:
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Michael Strauss authored
[WHY] Clocks don't get recalculated in 0 stream/0 pipe configs, blocking S0i3 if dcfclk gets high enough [HOW] Create DCN31 copy of DCN30 bandwidth validation func which doesn't entirely skip validation in 0 pipe scenarios Override dcfclk to vlevel 0/min value during validation if pipe count is 0 Reviewed-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Jude Shih authored
[WHY] To add support for HPD interrupt handling from DMUB. HPD interrupt could be triggered from outbox1 from DMUB [HOW] 1) Use queue_work to handle hpd task from outbox1 2) Add handle_hpd_irq_helper to share interrupt handling code between legacy and DMUB HPD from outbox1 3) Added DMUB HPD handling in dmub_srv_stat_get_notification(). HPD handling callback function and wake up the DMUB thread. Reviewed-by:
Jude Shih <shenshih@amd.com> Tested-by:
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Josip Pavic authored
[Why] Some ABM registers don't exist on DCN 3.01, so are missing from its register offset list. However, this list was copied to later versions of DCN that do have these registers. As a result, they're inaccessible from the driver on those DCN versions even though they exist. [How] Add the missing ABM register offsets to DCN 3.02+ Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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Jerry Zuo authored
1. Retrieve 128/132b link cap. 2. 128/132b link training and payload allocation. 3. UHBR10 link rate support. [squash in warning fixes - Alex] Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Jerry Zuo authored
Parse DP2 encoder caps and hpo instance from bios Signed-off-by:
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Jerry Zuo authored
HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | | v v v | +---------------------+ | | HPO Stream Encoder | | +---------------------+ | | | v | +--------------------+ | | HPO Link Encoder | | +--------------------+ | | v ===============|============= v +------------------+ | DIO Output Mux | +------------------+ | v +-----+ | PHY | +-----+ | PHYD32CLK[0] v +------+ | DCCG | +------+ | v SYMCLK32 Signed-off-by: -
Jerry Zuo authored
HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | | v v v | +---------------------+ | | HPO Stream Encoder | | +---------------------+ | | | v | +--------------------+ | | HPO Link Encoder | v +--------------------+ [squash in warning fixes - Alex] Signed-off-by: -
Jerry Zuo authored
HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | v v v v +----------------------+ | HPO Stream Encoder | +----------------------+ [squash in warning fixes - Alex] Signed-off-by: -
Jerry Zuo authored
HW Blocks: +-----+ | HDA | +-----+ | | HPO ===============|============= | v | +-----+ | | APG | v +-----+ Signed-off-by:
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