- Jun 15, 2023
-
-
Alex Deucher authored
This reverts commit 651a0d1c. This isn't quite right. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Wang Ming authored
Identify issues that arise by using the tests/doubletest.cocci semantic patch. Need to remove duplicate expression in if statement. Signed-off-by:
Wang Ming <machel@vivo.com> Reviewed-by:
Ammar Faizi <ammarfaizi2@gnuweeb.org> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Wayne Lin authored
[Why] The sequence for collecting down_reply from source perspective should be: Request_n->repeat (get partial reply of Request_n->clear message ready flag to ack DPRX that the message is received) till all partial replies for Request_n are received->new Request_n+1. Now there is chance that drm_dp_mst_hpd_irq() will fire new down request in the tx queue when the down reply is incomplete. Source is restricted to generate interveleaved message transactions so we should avoid it. Also, while assembling partial reply packets, reading out DPCD DOWN_REP Sideband MSG buffer + clearing DOWN_REP_MSG_RDY flag should be wrapped up as a complete operation for reading out a reply packet. Kicking off a new request before clearing DOWN_REP_MSG_RDY flag might be risky. e.g. If the reply of the new request has overwritten the DPRX DOWN_REP Sideband MSG buffer before source writing one to clear DOWN_REP_MSG_RDY flag, source then unintentionally flushes the reply for the new request. Should handle the up request in the same way. [How] Separete drm_dp_mst_hpd_irq() into 2 steps. After acking the MST IRQ event, driver calls drm_dp_mst_hpd_irq_send_new_request() and might trigger drm_dp_mst_kick_tx() only when there is no on going message transaction. Changes since v1: * Reworked on review comments received -> Adjust the fix to let driver explicitly kick off new down request when mst irq event is handled and acked -> Adjust the commit message Changes since v2: * Adjust the commit message * Adjust the naming of the divided 2 functions and add a new input parameter "ack". * Adjust code flow as per review comments. Changes since v3: * Update the function description of drm_dp_mst_hpd_irq_handle_event Changes since v4: * Change ack of drm_dp_mst_hpd_irq_handle_event() to be an array align the size of esi[] Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
Lyude Paul <lyude@redhat.com> Acked-by:
Jani Nikula <jani.nikula@intel.com> Cc: stable@vger.kernel.org
-
PhilipY authored
If hmm_range_fault returns -EBUSY, we should call hmm_range_fault again to validate the remaining pages. On one system with NUMA auto balancing enabled, hmm_range_fault takes 6 seconds for 1GB range because CPU migrate the range one page at a time. To be safe, increase timeout value to 1 second for 128MB range. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com>
-
PhilipY authored
To extend UTCL2 reach. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com>
-
Alex Deucher authored
DDR5 channels are 32 bit rather than 64, report the width properly in the log. Link: drm/amd#2468 Acked-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
lijo lazar authored
Set compute partition mode interface in NBIO is no longer used. Remove the only implementation from NBIO v7.9 Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com>
-
lijo lazar authored
Use PSP firmware interface for switching compute partitions. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com>
-
lijo lazar authored
PARTITION_MODE field in PARTITION_COMPUTE_STATUS register is defined as below by firmware. SPX = 0, DPX = 1, TPX = 2, QPX = 3, CPX = 4 Change driver definition accordingly. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com>
-
Christian König authored
It's perfectly possible that the BO is about to be destroyed and doesn't have a backing store associated with it. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Acked-by: Guchun Chen <guchun.chen@amd.com> for this series. Tested-by:
Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
-
Christian König authored
We need to grab the lock of the BO or otherwise can run into a crash when we try to inspect the current location. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Acked-by: Guchun Chen <guchun.chen@amd.com> for this series. Tested-by:
Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
-
stanley yang authored
Do not compare injection address with mc_vram_size if mc_vram_size is zero. Change-Id: I5555f29e6a023652d9992b0bd5089369f48e7ce6 Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com>
-
stanley yang authored
Using "is_app_apu" to identify device in the native APU mode or carveout mode. Change-Id: Ib17b1cdfaf70129b06bea58b494e59c7a15a7366 Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com>
-
Candice Li authored
Add disabled channel number to ras init flags. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com>
-
Candice Li authored
Update total channel number for umc v8_10. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com>
-
Candice Li authored
Update eccinfo table structure according to smu v13_0_0 interface. v2: Calculate array size instead of using macro definition. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com>
-
- Jun 14, 2023
-
-
SRINIVASAN SHANMUGAM authored
Fixes the following gcc with W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3483: warning: Cannot understand * ******************************************************************************* drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:4204: warning: Cannot understand * ******************************************************************************* Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
-
jokim-amd authored
Queue count should decrement on queue destruction regardless of HWS support type. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com>
-
- Jun 13, 2023
-
-
Tim Huang authored
This patch enables following UMD stable Pstates profile levels for power_dpm_force_performance_level interface. - profile_peak - profile_min_sclk - profile_standard Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com>
-
SRINIVASAN SHANMUGAM authored
Fixes the following gcc with W=1: drivers/gpu/drm/radeon/radeon_atpx_handler.c:64:6: warning: no previous prototype for ‘radeon_has_atpx’ [-Wmissing-prototypes] 64 | bool 4(void) { | ^~~~~~~~~~~~~~~ drivers/gpu/drm/radeon/radeon_atpx_handler.c:68:6: warning: no previous prototype for ‘radeon_has_atpx_dgpu_power_cntl’ [-Wmissing-prototypes] 68 | bool radeon_has_atpx_dgpu_power_cntl(void) { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/radeon/radeon_atpx_handler.c:72:6: warning: no previous prototype for ‘radeon_is_atpx_hybrid’ [-Wmissing-prototypes] 72 | bool radeon_is_atpx_hybrid(void) { | ^~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/radeon/radeon_atpx_handler.c:77:6: warning: no previous prototype for ‘radeon_atpx_dgpu_req_power_for_displays’ [-Wmissing-prototypes] 77 | bool radeon_atpx_dgpu_req_power_for_displays(void) { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/radeon/radeon_atpx_handler.c:596:6: warning: no previous prototype for ‘radeon_register_atpx_handler’ [-Wmissing-prototypes] 596 | void radeon_register_atpx_handler(void) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/radeon/radeon_atpx_handler.c:614:6: warning: no previous prototype for ‘radeon_unregister_atpx_handler’ [-Wmissing-prototypes] 614 | void radeon_unregister_atpx_handler(void) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/radeon/radeon_atpx_handler.c:159: warning: expecting prototype for radeon_atpx_validate_functions(). Prototype was for radeon_atpx_validate() instead Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com>
-
Luben Tuikov authored
The fixed commit listed in the Fixes tag below, introduced a bug in amdgpu_ras.c::amdgpu_reserve_page_direct(), in that when introducing the new amdgpu_umc_fill_error_record() and internally in that new function the physical address (argument "uint64_t retired_page"--wrong name) is right-shifted by AMDGPU_GPU_PAGE_SHIFT. Thus, in amdgpu_reserve_page_direct() when we pass "address" to that new function, we should NOT right-shift it, since this results, erroneously, in the page address to be 0 for first 2^(2*AMDGPU_GPU_PAGE_SHIFT) memory addresses. This commit fixes this bug. Cc: Tao Zhou <tao.zhou1@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Alex Deucher <Alexander.Deucher@amd.com> Fixes: 400013b2 ("drm/amdgpu: add umc_fill_error_record to make code more simple") Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Link: https://lore.kernel.org/r/20230610113536.10621-1-luben.tuikov@amd.com Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com>
-
Alex Deucher authored
The wptr needs to be incremented at at least 64 dword intervals, use 256 to align with windows. This should fix potential hangs with unaligned updates. Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Luben Tuikov authored
Report the number of records stored in the RAS EEPROM table in debugfs. This can be used by user-space to calculate the capacity of the RAS EEPROM table since "bad_page_cnt_threshold" is also reported in the same place in debugfs. See commit reference 7fb64071 (drm/amdgpu: Add bad_page_cnt_threshold to debugfs, 2021-04-13). ras_num_recs can already be inferred by dumping the RAS EEPROM table, also in the same debugfs location, see commit reference c65b0805 (drm/amdgpu: RAS EEPROM table is now in debugfs, 2021-04-08). This commit makes it an integer value easily shown in a single file. Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Tao Zhou <tao.zhou1@amd.com> Cc: Stanley Yang <Stanley.Yang@amd.com> Cc: John Clements <john.clements@amd.com> Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Link: https://lore.kernel.org/r/20230603051043.211548-1-luben.tuikov@amd.com Acked-by:
Alex Deucher <Alexander.Deucher@amd.com>
-
Mukul Joshi authored
Remove DUMMY_VRAM_SIZE as it is not needed and can result in reporting incorrect memory size. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com>
-
lijo lazar authored
Release ECC irq only if irq is enabled - only when RAS feature is enabled ECC irq gets enabled. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com>
-
Likun Gao authored
Spirom update typically requires extremely long duration for command execution, and special helper function to wait for it completion. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com>
-
SRINIVASAN SHANMUGAM authored
Fixes the following W=1 kernel build warning: display/dc/dcn10/dcn10_optc.c:45: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * apply_front_porch_workaround TODO FPGA still need? display/dc/dcn10/dcn10_optc.c:136: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * program_timing_generator used by mode timing set display/dc/dcn10/dcn10_optc.c:391: warning: Function parameter or member 'optc' not described in 'optc1_set_timing_double_buffer' display/dc/dcn10/dcn10_optc.c:391: warning: Function parameter or member 'enable' not described in 'optc1_set_timing_double_buffer' display/dc/dcn10/dcn10_optc.c:404: warning: Function parameter or member 'optc' not described in 'optc1_unblank_crtc' display/dc/dcn10/dcn10_optc.c:404: warning: expecting prototype for unblank_crtc(). Prototype was for optc1_unblank_crtc() instead display/dc/dcn10/dcn10_optc.c:427: warning: Function parameter or member 'optc' not described in 'optc1_blank_crtc' display/dc/dcn10/dcn10_optc.c:427: warning: expecting prototype for blank_crtc(). Prototype was for optc1_blank_crtc() instead display/dc/dcn10/dcn10_optc.c:496: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Enable CRTC display/dc/dcn10/dcn10_optc.c:895: warning: Cannot understand ***************************************************************************** on line 895 - I thought it was a doc line Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
-
SRINIVASAN SHANMUGAM authored
Fixes the following gcc with W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:285: warning: Function parameter or member 'dc' not described in 'dcn32_determine_det_override' drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:285: warning: Function parameter or member 'context' not described in 'dcn32_determine_det_override' drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:285: warning: Function parameter or member 'pipes' not described in 'dcn32_determine_det_override' drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:624: warning: Cannot understand * ***************************************************************** drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:676: warning: Cannot understand * ***************************************************************** Cc: Alvin Lee <alvin.lee2@amd.com> Cc: Stylon Wang <stylon.wang@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
Alvin Lee <alvin.lee2@amd.com>
-
SRINIVASAN SHANMUGAM authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:109: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Enable CRTC Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
-
SRINIVASAN SHANMUGAM authored
Fixes the following gcc with W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:872: warning: Excess function parameter 'drr_pipe' description in 'subvp_drr_schedulable' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:1030: warning: Cannot understand * **************************************************** Cc: Stylon Wang <stylon.wang@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
-
SRINIVASAN SHANMUGAM authored
Fixes the following W=1 kernel build warning: display/dc/dcn10/dcn10_opp.c:52: warning: Function parameter or member 'oppn10' not described in 'opp1_set_truncation' display/dc/dcn10/dcn10_opp.c:52: warning: Function parameter or member 'params' not described in 'opp1_set_truncation' display/dc/dcn10/dcn10_opp.c:52: warning: expecting prototype for set_truncation(). Prototype was for opp1_set_truncation() instead display/dc/dcn10/dcn10_opp.c:161: warning: Function parameter or member 'oppn10' not described in 'opp1_set_pixel_encoding' display/dc/dcn10/dcn10_opp.c:161: warning: Function parameter or member 'params' not described in 'opp1_set_pixel_encoding' display/dc/dcn10/dcn10_opp.c:161: warning: expecting prototype for set_pixel_encoding(). Prototype was for opp1_set_pixel_encoding() instead display/dc/dcn10/dcn10_opp.c:183: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Set Clamping Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
-
SRINIVASAN SHANMUGAM authored
drm/amdgpu: Add missing function parameter 'optc' & 'enable' to kdoc in optc3_set_timing_double_buffer() Fixes the following gcc with W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:285: warning: Function parameter or member 'optc' not described in 'optc3_set_timing_double_buffer' drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:285: warning: Function parameter or member 'enable' not described in 'optc3_set_timing_double_buffer' Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
-
majun258 authored
Modify the debug information and print the clien id for these interrupts as well. Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com>
-
Ruili Ji authored
Flag trap_en should be enabled for trap handler. Signed-off-by:
Ruili Ji <ruiliji2@amd.com> Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com>
-
- Jun 12, 2023
-
-
James Zhu authored
Bump the minor version to declare event age tracking feature is now available. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com>
-
James Zhu authored
Update user space last_event_age when event age is enabled. It is only for KFD_EVENT_TYPE_SIGNAL which is checked by user space. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com>
-
James Zhu authored
Set waiter's activated flag true when event age unmatchs with last_event_age. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com>
-
Alex Deucher authored
Don't free the memory if we are hitting this as part of suspend. This way we don't free any memory during suspend; see amdgpu_bo_free_kernel(). The memory will be freed in the first non-suspend modeset or when the driver is torn down. Link: drm/amd#2568 Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
James Zhu authored
Add event_age tracking when receiving interrupt. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com>
-
James Zhu authored
Add event age tracking Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com>
-