Skip to content
Snippets Groups Projects
Commit f2510355 authored by ganglxie's avatar ganglxie Committed by Alex Deucher
Browse files

drm/amdgpu: Save nps to eeprom


nps info saved together with bad page makes bad page parsing more efficient

Signed-off-by: default avatarganglxie <ganglxie@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ce615fe3
No related merge requests found
...@@ -852,6 +852,7 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, ...@@ -852,6 +852,7 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
{ {
struct amdgpu_device *adev = to_amdgpu_device(control); struct amdgpu_device *adev = to_amdgpu_device(control);
int res, i; int res, i;
uint64_t nps = AMDGPU_NPS1_PARTITION_MODE;
if (!__is_ras_eeprom_supported(adev)) if (!__is_ras_eeprom_supported(adev))
return 0; return 0;
...@@ -865,9 +866,12 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, ...@@ -865,9 +866,12 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
return -EINVAL; return -EINVAL;
} }
if (adev->gmc.gmc_funcs->query_mem_partition_mode)
nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
/* set the new channel index flag */ /* set the new channel index flag */
for (i = 0; i < num; i++) for (i = 0; i < num; i++)
record[i].retired_page |= UMC_CHANNEL_IDX_V2; record[i].retired_page |= (nps << UMC_NPS_SHIFT);
mutex_lock(&control->ras_tbl_mutex); mutex_lock(&control->ras_tbl_mutex);
...@@ -881,7 +885,7 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, ...@@ -881,7 +885,7 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
/* clear channel index flag, the flag is only saved on eeprom */ /* clear channel index flag, the flag is only saved on eeprom */
for (i = 0; i < num; i++) for (i = 0; i < num; i++)
record[i].retired_page &= ~UMC_CHANNEL_IDX_V2; record[i].retired_page &= ~(nps << UMC_NPS_SHIFT);
return res; return res;
} }
......
...@@ -71,6 +71,13 @@ ...@@ -71,6 +71,13 @@
*/ */
#define UMC_CHANNEL_IDX_V2 BIT_ULL(47) #define UMC_CHANNEL_IDX_V2 BIT_ULL(47)
/*
* save nps value to eeprom_table_record.retired_page[47:40],
* the channel index flag above will be retired.
*/
#define UMC_NPS_SHIFT 40
#define UMC_NPS_MASK 0xffULL
typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst, typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst,
uint32_t umc_inst, uint32_t ch_inst, void *data); uint32_t umc_inst, uint32_t ch_inst, void *data);
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment