- Jul 01, 2008
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(cherry picked from commit d5ae19eb)
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- May 28, 2008
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Dave Airlie authored
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Dave Airlie authored
This will be the next release of libdrm as 2.3.1, Mesa needs to deal with this for 7.1.
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Dave Airlie authored
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Dave Airlie authored
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Dave Airlie authored
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- May 27, 2008
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Alex Deucher authored
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Also remove an unreachable unlock.
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The i915 driver now works again.
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Emma Anholt authored
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- May 22, 2008
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Dave Airlie authored
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Dave Airlie authored
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- May 21, 2008
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Dave Airlie authored
The new display controller has the vblank interrupts in a different place. Add support for vbl interrupts for these chips
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- May 17, 2008
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Dave Airlie authored
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- May 14, 2008
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Dave Airlie authored
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Dave Airlie authored
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Dave Airlie authored
This reverts commit bc0836e1. tree has some kref hacks in it - oops
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Dave Airlie authored
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Dave Airlie authored
Thanks to Alex for supplying this info.
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Alex Deucher authored
RS400 (intel based IGP) and RS480 (AMD based IGP) have different MC and GART setups. Currently we only support RS480.
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- May 12, 2008
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Alex Deucher authored
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Alex Deucher authored
Similar (broken) code in mesa needs to be removed
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
first step in merging rs4xx/rs6xx gart setup
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Alex Deucher authored
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- May 07, 2008
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Dave Airlie authored
The kernel has removed nopage so move the old nopage codepaths into a compat vm file and switch to using the fault paths. nopfn is on its way out in the future also, so we should switch to using fault for that path as well soon
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- May 05, 2008
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Dave Airlie authored
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- May 01, 2008
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Ben Skeggs authored
No solid idea about what these 2 bits do, but nv50 can now survive a few PGRAPH exceptions just as nv40 does :)
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Ben Skeggs authored
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Ben Skeggs authored
This is possibly temporary. I can trigger an unending IRQ storm on G8x in some circumstances, and have no idea how to handle that particular PFIFO exception correctly yet.
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Ben Skeggs authored
Doesn't fix any issue I've seen, but is a potential issue if a FIFO IRQ occurs during channel creation/takedown.
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