radv: fix missing cache flushes when clearing HTILE levels on GFX10+
The driver should accumulate the cache flush bits because if it uses CP DMA for clearing the last level, it won't flush. Found by inspection. Cc: 21.2 mesa-stable Signed-off-by:Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!12170> (cherry picked from commit ad83c06a)