- May 18, 2018
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Dylan Baker authored
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Dylan Baker authored
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- May 11, 2018
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Dylan Baker authored
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Jan Vesely authored
Fixes memory leak on module unload. CC: <mesa-stable@lists.freedesktop.org> Signed-off-by:
Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 58272c1a)
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Marek Olšák authored
Fixes: 6d19120d "radeonsi/gfx9: workaround for INTERP with indirect indexing" Cc: 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit 597b9e88)
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Since size can be 3, 4 or GL_BGRA we need to keep these glGet types as TYPE_INT, not TYPE_UBYTE. Fixes: d07466fe ("mesa: fix glGetInteger/Float/etc queries for vertex arrays attribs") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106462 cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Mathias Fröhlich <mathias.froehlich@web.de> (cherry picked from commit e4211b36)
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The vertex array Size and Stride attributes are now ubyte and short, respectively. The glGet code needed to be updated to handle those types, but wasn't. Fixes the new piglit test gl-1.5-get-array-attribs test. v2: fix inadvertant whitespace change, change COLOR_ARRAY_SIZE to UBYTE, misc fixes suggested by Justin Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106450 Fixes: d5f42f96 ("mesa: shrink size of gl_array_attributes (v2)") Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Mathias Fröhlich <mathias.froehlich@web.de> Reviewed-by:
Jordan Justen <jordan.l.justen@intel.com> (cherry picked from commit d07466fe)
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- May 10, 2018
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Faith Ekstrand authored
From the bspec docs for "Indirect State Pointers Disable": "At the completion of the post-sync operation associated with this pipe control packet, the indirect state pointers in the hardware are considered invalid" So the ISP disable is a post-sync type of operation which means that it should be combined with a CS stall. Without this, the simulator throws an error. Fixes: 766d801c "anv: emit pixel scoreboard stall before ISP disable" Fixes: f536097f "i965: require pixel scoreboard stall prior to ISP disable" Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit a8a740f2)
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We want to make sure that all indirect state data has been loaded into the EUs before disable the pointers. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Rafael Antognolli <rafael.antognolli@intel.com> Fixes: 78c125af ("anv/gen10: Ignore push constant packets during context restore.") (cherry picked from commit 766d801c)
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Invalidating the indirect state pointers might affect a previously scheduled & still running 3DPRIMITIVE (causing page fault). So stall on pixel scoreboard before that. v2: Fix compile issue :( v3: Stall on pixel scoreboard v4: Drop the post sync operation (Lionel) Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Rafael Antognolli <rafael.antognolli@intel.com> Fixes: ca19ee33 ("i965/gen10: Ignore push constant packets during context restore.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106243 (cherry picked from commit f536097f)
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Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 2dc29e09 ("i965: Don't leak blorp on Gen4-5.") Reviewed-by:
Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> (cherry picked from commit 3853f1c6)
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Jan Vesely authored
Fixes memory leak on module unload. v2: Use util_hash_table helper function CC: <mesa-stable@lists.freedesktop.org> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
Jan Vesely <jan.vesely@rutgers.edu> (cherry picked from commit 45dfa6f4)
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Jan Vesely authored
CC: <mesa-stable@lists.freedesktop.org> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
Jan Vesely <jan.vesely@rutgers.edu> (cherry picked from commit d146768d)
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If you have an indirect access to a constant buffer on r600/eg use a vertex fetch in the shader. However apps have expected behaviour on those out of bounds accessess (even if illegal). If the constants were being uploaded as part of a larger upload buffer, we'd set the range of allowed access to a lot larger than required so apps would get values back from other parts of the upload buffer instead of the expected out of bounds access. This fixes rendering bugs in Trine and Witcher 1, thanks to iive for nagging me effectively until I figured it out :-) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91808 Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> (cherry picked from commit ce027ac5)
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Out of tree builds can try to write into a directory that doesn't exist yet: | Traceback (most recent call last): | File "../../../mesa-18.0.2/src/intel/vulkan/anv_icd.py", line 46, in <module> | with open(args.out, 'w') as f: | IOError: [Errno 2] No such file or directory: 'vulkan/intel_icd.x86_64.json' | Makefile:4882: recipe for target 'vulkan/intel_icd.x86_64.json' failed Add missing MKDIR_GEN calls to solve this. Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by:
Matt Turner <mattst88@gmail.com> (cherry picked from commit 1755654d)
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CC: <mesa-stable@lists.freedesktop.org> Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Tapani Pälli <tapani.palli@intel.com> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> (cherry picked from commit 5ac16ed0)
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- May 09, 2018
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Michel Dänzer authored
And only free no longer needed back buffers there as well. We want to stick to the same back buffer throughout a frame, otherwise we can run into various issues. Bugzilla: https://bugs.freedesktop.org/105906 Bugzilla: https://bugs.freedesktop.org/106399 Fixes: 3160cb86 "egl/x11: Re-allocate buffers if format is suboptimal" Reported-by:
Sergii Romantsov <sergii.romantsov@globallogic.com> Tested-by:
Eero Tamminen <eero.t.tamminen@intel.com> Acked-by:
Daniel Stone <daniels@collabora.com> (cherry picked from commit 6f81e07e)
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Jan Vesely authored
CC: <mesa-stable@lists.freedesktop.org> Signed-off-by:
Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 0783399d)
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Change the size of the bitset from 128 bits to 96. This works around an apparent GCC 5.4 bug in which bad SSE code is generated, leading to a crash in ast_type_qualifier::validate_in_qualifier() (ast_type.cpp:654). This can be repro'd with the Piglit test tests/spec/glsl-1.50/execution/ varying-struct-basic-gs-fs.shader_test Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=105497 Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Charmaine Lee <charmainel@vmware.com> Tested-by:
Charmaine Lee <charmainel@vmware.com> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> (cherry picked from commit 901db25d)
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- May 08, 2018
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Jan Vesely authored
CC: <mesa-stable@lists.freedesktop.org> Signed-off-by:
Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit a9e4be92)
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Jan Vesely authored
Signed-off-by:
Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit ea1fff44)
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I forgot to change the assert in the second helper function in a previous change. This hit the assert() on a Broadwell platform with 1 slice, 3 subslices but all EUs disabled in subslice 1 & 2. Fixes: c1900f5b ("intel: devinfo: add helper functions to fill fusing masks values") Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 3cdf1bf9)
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We used to only initialize BLORP on Gen6+. When we added it on Gen4-5, we forgot to destroy it unconditionally. Fixes: 752d7af7 (i965: Add blorp support for gen4-5) Reviewed-by:
Matt Turner <mattst88@gmail.com> (cherry picked from commit 2dc29e09)
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This was setting the LINEAR modifier if neither the X server nor the driver supported modifiers. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106180 Fixes: c80c08e2 "vulkan/wsi/x11: Add support for DRI3 v1.2" CC: 18.1 <mesa-stable@lists.freedesktop.org> Tested-by:
Abel Garcia Dorta <mercuriete@gmail.com> Acked-by:
Daniel Stone <daniels@collabora.com> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit b17cfb08)
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Jan Vesely authored
CC: <mesa-stable@lists.freedesktop.org> Signed-off-by:
Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit a1e8fcce)
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- May 07, 2018
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Found by inspection, so I made a piglit test too. Signed-off-by:
Ian Romanick <ian.d.romanick@intel.com> Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit f2db3be6)
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- May 04, 2018
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Dylan Baker authored
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- May 03, 2018
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This behaviour was changed in 1e5b09f4. The commit message for that says it is just a “tidy up” so my assumption is that the behaviour change was a mistake. It’s a little hard to decipher looking at the diff, but the previous code before that patch was: if (builtin == SpvBuiltInFragCoord || builtin == SpvBuiltInSamplePosition) nir_var->data.origin_upper_left = b->origin_upper_left; if (builtin == SpvBuiltInFragCoord) nir_var->data.pixel_center_integer = b->pixel_center_integer; After the patch the code was: case SpvBuiltInSamplePosition: nir_var->data.origin_upper_left = b->origin_upper_left; /* fallthrough */ case SpvBuiltInFragCoord: nir_var->data.pixel_center_integer = b->pixel_center_integer; break; Before the patch origin_upper_left affected both builtins and pixel_center_integer only affected FragCoord. After the patch origin_upper_left only affects SamplePosition and pixel_center_integer affects both variables. This patch tries to restore the previous behaviour by changing the code to: case SpvBuiltInFragCoord: nir_var->data.pixel_center_integer = b->pixel_center_integer; /* fallthrough */ case SpvBuiltInSamplePosition: nir_var->data.origin_upper_left = b->origin_upper_left; break; This change will be important for ARB_gl_spirv which is meant to support OriginLowerLeft. Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Reviewed-by:
Anuj Phogat <anuj.phogat@gmail.com> Fixes: 1e5b09f4 "spirv: Tidy some repeated if checks..." (cherry picked from commit e17d0ccb)
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Similar to swap_available path send invalidate to the driver because egl/X11 is not watching for for server's invalidate events. The dri2_copy_region path is trigerred when server supports DRI2 version minor 1. Tested with piglit egl tests for regression. V2: Move invalidate from dri2_copy_region to swap_buffer common. Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by:
Deepak Rawat <drawat@vmware.com> Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com> Acked-by:
Michel Dänzer <michel.daenzer@amd.com> (cherry picked from commit 9a21c961)
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16-bit immediates need to replicate the 16-bit immediate value in both words of the 32-bit value. This needs to be careful to avoid sign-extension, which the previous implementation was not handling properly. For example, with the previous implementation, storing the value -3 would generate imm.d = 0xfffffffd due to signed integer sign extension, which is not correct. Instead, we should cast to uint16_t, which gives us the correct result: imm.ud = 0xfffdfffd. We only had a couple of cases hitting this path in the driver until now, one with value -1, which would work since all bits are one in this case, and another with value -2 in brw_clip_tri(), which would hit the aforementioned issue (this case only affects gen4 although we are not aware of whether this was causing an actual bug somewhere). v2: Make explicit uint32_t casting for left shift (Jason Ekstrand) Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Cc: "18.0 18.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit f0e6dace)
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From Intel Skylake PRM, vol 07, "Immediate" section (page 768): "For a word, unsigned word, or half-float immediate data, software must replicate the same 16-bit immediate value to both the lower word and the high word of the 32-bit immediate field in a GEN instruction." This fixes the int16/uint16 negate and abs immediates that weren't taking into account the replication in lower and upper words. v2: Integer cases are different to Float cases. (Jason Ekstrand) Included reference to PRM (Jose Maria Casanova) v3: Make explicit uint32_t casting for left shift (Jason Ekstrand) Split half float implementation. (Jason Ekstrand) Fix brw_abs_immediate (Jose Maria Casanova) Cc: "18.0 18.1" <mesa-stable@lists.freedesktop.org> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 2a76f03c)
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This fixes dEQP-VK.api.device_init.create_instance_invalid_api_version CC: 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 467c562a)
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Apparently the somewhere between 1.1.70 and 1.1.73 the loader started depending on this. The loader then creates a 1.0 instance, which gets into funny situation because we have a 1.1 device. No idea how to do line wrapping in Mako though, my random guesses did not work. CC: 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 9267ff98)
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- May 02, 2018
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Both the internal documentation and the results of testing this in the CI suggest that this is unnecessary. Add the fixes tag because this reduces an internal benchmark's startup time by about 17 seconds (reported by Eero). Fixes: 710b1d2e "i965/tex_image: Flush certain subnormal ASTC channel values" Tested-by:
Eero Tamminen <eero.t.tamminen@intel.com> Acked-by:
Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 3e56e464)
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Faith Ekstrand authored
Fixes: cbab2d1d Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit d216ffc6)
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Previously before fb077b07, the LOD parameter was being used in place of the sample index, which would only copy the first sample to all samples in the destination image. After that multisample image copies wouldn't copy anything from my observations. This fixes some copy_and_blit CTS tests. v3.1: - set lod to 0 for nir_txf_ms (Samuel) v2: - use GLSL_SAMPLER_DIM_MS instead of 2D (Samuel) - updated commit description (Samuel) Fix this properly by copying each sample in a separate radv_CmdDraw and using a pipeline with the correct rasterizationSamples for the destination image. Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 97d57ef9)
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- May 01, 2018
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Only count color attachments twice if resolves are used, also account for the depth stencil attachment if present. Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit d8db5986)
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A bo's ref_count was not being initialized when imported from an fd. Therefore, we would fail to free the resource during VkFreeMemory(). This patch fixes applications like hifi VR in threaded mode, which perform frequent imports/releases of IPC shared memory. Signed-off-by:
Andres Rodriguez <andresx7@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org> (cherry picked from commit f56e22e4)
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- Apr 30, 2018
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The blit here involves scaling since it's copying from I8 format to R8G8 format. Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it looks that GPU always uses the second half as source. Currently we use "1" as the start point of x for R, then causing 1 source pixel of U component shift to right. So "-1" should be the start point for U component. Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 1c5f4f4e)
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