- May 07, 2018
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Juan A. Suárez authored
Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com>
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Juan A. Suárez authored
Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com>
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- May 02, 2018
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Previous bit-fields assignments are incorrect and will result certain mpeg4 decode failed due to wrong flag values. This patch fixes these assignments. Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> (cherry picked from commit deba56ac)
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Both the internal documentation and the results of testing this in the CI suggest that this is unnecessary. Add the fixes tag because this reduces an internal benchmark's startup time by about 17 seconds (reported by Eero). Fixes: 710b1d2e "i965/tex_image: Flush certain subnormal ASTC channel values" Tested-by:
Eero Tamminen <eero.t.tamminen@intel.com> Acked-by:
Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 3e56e464)
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Only count color attachments twice if resolves are used, also account for the depth stencil attachment if present. Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit d8db5986)
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A bo's ref_count was not being initialized when imported from an fd. Therefore, we would fail to free the resource during VkFreeMemory(). This patch fixes applications like hifi VR in threaded mode, which perform frequent imports/releases of IPC shared memory. Signed-off-by:
Andres Rodriguez <andresx7@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org> (cherry picked from commit f56e22e4)
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- Apr 30, 2018
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The blit here involves scaling since it's copying from I8 format to R8G8 format. Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it looks that GPU always uses the second half as source. Currently we use "1" as the start point of x for R, then causing 1 source pixel of U component shift to right. So "-1" should be the start point for U component. Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 1c5f4f4e) [Juan A. Suarez: apply patch in src/gallium/state_trackers/omx_bellagio/vid_enc.c] Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/gallium/state_trackers/omx/vid_enc_common.c
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The driver may have a reference on the separate stencil buffer for some reason (like an unflushed job using it), so we can't directly free the resource and should instead just decrement the refcount that we own. Fixes double-free in KHR-GLES3.packed_depth_stencil.blit.depth32f_stencil8 on vc5. Fixes: e94eb5e6 ("gallium/util: add u_transfer_helper") Reviewed-by:
Rob Clark <robdclark@gmail.com> (cherry picked from commit 069c409f)
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and clean up the conditions. Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 6d19120d)
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Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit 7083ac72)
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Previously, we only tried to ensure that we didn't shrink either end below what was already handed out. However, due to the way we handle relocations with block pools, we can't shrink the back end at all. It's probably best to not shrink in either direction. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105374 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106147 Tested-by:
Eero Tamminen <eero.t.tamminen@intel.com> Reviewed-by:
Scott D Phillips <scott.d.phillips@intel.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 3db93f91)
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Juan A. Suárez authored
Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com>
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- Apr 28, 2018
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Juan A. Suárez authored
Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com>
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Juan A. Suárez authored
Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com>
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Juan A. Suárez authored
Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com>
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- Apr 25, 2018
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Since mesa_classic is build-on-demand the tests will create a demand and add a bunch of extra compilation. Fixes: 43a6e849 ("meson: build mesa test.") Signed-off-by:
Dylan Baker <dylan.c.baker@intel.com> Reviewed-by:
Eric Anholt <eric@anholt.net> (cherry picked from commit aaab6242)
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The SI family doesn't support chaining which means the maximum size in dwords per CS is limited. When that limit was reached we failed to submit the CS and the application crashed. This patch allows to submit up to 4 IBs which is currently the limit, but recent amdgpu supports more than that. Please note that we can reach the limit of 4 IBs per submit but currently we can't improve that. The only solution is to upgrade libdrm. That will be improved later but for now this should fix crashes on SI or when using RADV_DEBUG=noibs. Fixes: 36cb5508 ("radv/winsys: Fail early on overgrown cs.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105775 Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com>
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Otherwise the scheduler can move the writes after the reads. Signed-off-by:
Ian Romanick <ian.d.romanick@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95009 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95012 Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Tested-by:
Mark Janes <mark.a.janes@intel.com> Cc: Clayton A Craft <clayton.a.craft@intel.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 0d5ce25c)
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- Apr 24, 2018
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This fixes -Ddri-drivers-path, -Dvdpau-libs-path, etc. with DESTDIR when those paths are absolute. Currently due to the way python's os.path.join handles absolute paths these will ignore DESTDIR, which is bad. This fixes them to be relative to DESTDIR if that is set. Fixes: 3218056e ("meson: Build i965 and dri stack") Signed-off-by:
Dylan Baker <dylan.c.baker@intel.com> (cherry picked from commit ae3f45c1)
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They are send messages and this makes size_read() and mlen agree. For both of these opcodes, the payload is just a dummy so mlen == 1 and this should decrease register pressure a bit. Reviewed-by:
Francisco Jerez <currojerez@riseup.net> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit de1f22d5)
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Juan A. Suárez authored
Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com>
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- Apr 23, 2018
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If an EGLSurface is created, made current and destroyed, and then a second EGLSurface is created. Then the second malloc in driCreateNewDrawable may return the same pointer address the first surface's drawable had. Consequently, when dri_make_current later tries to determine if it should update the texture_stamp it compares the surface's drawable pointer against the drawable in the last call to dri_make_current and assumes it's the same surface (which it isn't). When texture_stamp is left unset, then dri_st_framebuffer_validate thinks it has already called update_drawable_info for that drawable, leaving it unvalidated and this is when bad things starts to happen. In my case it manifested itself by the width and height of the surface being unset. This is fixed this by setting the pointer to NULL before freeing the surface. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106126 Signed-off-by:
Johan Klokkhammer Helsing <johan.helsing@qt.io> Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> (cherry picked from commit dab02dea)
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memcmp returns 0 when both swizzles are the same, which means we don't need any hardware swizzling. texture_format_needs_swiz should return true when the return value of the memcmp is non-zero. Fixes: 751ae6af ("etnaviv: add support for swizzled texture formats") Cc: mesa-stable@lists.freedesktop.org Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Tested-by:
Marek Vasut <marex@denx.de> Reviewed-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by:
Wladimir J. van der Laan <laanwj@gmail.com> (cherry picked from commit 52e93e30)
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Otherwise a lot of games complain about not having enough memory, and it is sort of local so this seems reasonable to me. CC: 18.0 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit e1df849c)
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Juan A. Suárez authored
This is a backport for 18.0 from 6ce400782c ("travis: radeonsi and radv need LLVM 4.0") that fixes Travis build with meson + vulkan. CC: 18.0 <mesa-stable@lists.freedesktop.org> Acked-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by:
Andres Gomez <agomez@igalia.com>
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brw_bo_alloc may round up our allocation size to the next bucket size. In this case, we would malloc a shadow buffer that was the original intended size, but use bo->size (the larger size) for all of our checks. This could cause us to run off the end of the shadow buffer. v2: Actually use the new BO size (caught by Lionel) Reported-by:
James Xiong <james.xiong@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: c7dcee58 (i965: Avoid problems from referencing orphaned BOs after growing.) (cherry picked from commit da25ae92)
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'scale[i]' can be non-integer. Original patch by Philip Rebohle. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106074 Fixes: 0f3de89a ("radv: Use the guard band.") Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Bas Niuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 893e19ef)
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We're not counting correctly with depth & stencil images. Additionally we need to move an assert that is meant just for color attachments. v2: Move an assert() (Reported by Craig) Change aspect mask checks (Francesco) Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: a62a9793 ("anv: enable multiple planes per image/imageView") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105994 Reviewed-by:
Nanley Chery <nanley.g.chery@intel.com> (cherry picked from commit 0a654701)
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Fixes: 04a8baad "mesa: refactor _mesa_PopDebugGroup and _mesa_free_errors_data" Reviewed-by:
Iago Toral Quiroga <itoral@igalia.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98281 (cherry picked from commit a63e69f5)
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When advertizing this extension, egl_dri2 uses the DRI2_RENDERER_QUERY extension to query whether an sRGB format is supported. That extension will query our driver with the BIND flag PIPE_BIND_RENDER_TARGET rather than PIPE_BIND_DISPLAY_TARGET which is used when building the configs. We only return the correct value for PIPE_BIND_DISPLAY_TARGET. The inconsistency causes EGL to crash at surface initialization if sRGB is not supported. Fix this by supporting both bind flags. Testing done: piglit egl_gl_colorspace srgb Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by:
Brian Paul <brianp@vmware.com> Reviewed-by:
Charmaine Lee <charmainel@vmware.com> (cherry picked from commit e0c08183)
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This fixes some piglits. Cc: 18.0 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit 7bd24d95)
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This packet causes the no-op IB detection to fail, so the IB is always submitted. Also fix the no-op IB detection by moving the begin call. Cc: 18.0 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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No clue how I missed those ... Fixes: 4503ff76 "ac/nir: Add workaround for GFX9 buffer views." CC: <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105320 Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit b0e3a9b1) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/amd/common/ac_nir_to_llvm.c
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- Apr 18, 2018
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Juan A. Suárez authored
Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com>
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Juan A. Suárez authored
Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com>
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Juan A. Suárez authored
Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com>
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- Apr 17, 2018
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It is present from libva 2.1 (VAAPI 1.1.0 or higher). Signed-off-by:
Mark Thompson <sw@jkqxz.net> Reviewed-by:
Christian König <christian.koenig@amd.com> (cherry picked from commit 768f1487)
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- Apr 14, 2018
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LLVM patch level is not included in HAVE_LLVM. Fixes: e6418ab1566d ("meson: build "radv" vulkan driver for radeon hardware") Reviewed-by:
Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by:
Dylan Baker <dylan.c.baker@intel.com> Signed-off-by:
Marc Dietrich <marvin24@gmx.de> (cherry picked from commit a2a1b0e7)
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- Apr 12, 2018
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num_dcc_levels means that DCC is supported, but this doesn't mean that it's enabled by the driver. Instead, we should rely on radv_image_has_dcc(). This fixes some multisample regressions since 0babc8e5 ("radv: fix picking the method for resolve subpass") on Vega. This is because the resolve method changed from HW to FS, but those fails are totally unexpected, so there might some differences between Polaris and Vega here. Fixes: 44fcf587 ("radv: Disable DCC for GENERAL layout and compute transfer dest.") Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 9eac4924) [Juan A. Suarez: do not call radv_image_has_dcc(), as it is not defined] Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com>
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