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Commit 72ccefb5 authored by Kenneth Graunke's avatar Kenneth Graunke
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iris: Use full ways for L3 cache setup on Icelake.


Anuj fixed this in i965 and anv, but the fix never landed in iris.
Fixes tessellation corruption on Icelake.  Thanks to Rafael for
bisecting this and tracking it down.

Fixes: d0996d5f iris: Emit default L3 config for the render pipeline
Reviewed-by: default avatarRafael Antognolli <rafael.antognolli@intel.com>
parent 3610081d
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......@@ -631,6 +631,7 @@ iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg,
* desirable behavior.
*/
reg.ErrorDetectionBehaviorControl = true;
reg.UseFullWays = true;
#endif
reg.URBAllocation = cfg->n[GEN_L3P_URB];
reg.ROAllocation = cfg->n[GEN_L3P_RO];
......
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