radeonsi: fix invalidating bindless buffer descriptors
The VA is stored at [4:5], not [0:1]. This invalidated all texture buffer descriptors when they were made resident in the current context. This removes few partial flushes and cache invalidations which are needed when updating a bindless descriptor on the fly with a WRITE_DATA packet. Signed-off-by:Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>