- Aug 07, 2017
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Emil Velikov authored
Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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Emil Velikov authored
Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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- Aug 02, 2017
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Copy/paste error was duplicating a gen_knobs.cpp rule. Fixes: 5079c277 ("swr: [scons] Fix windows build") Reviewed-by:
Emil Velikov <emil.velikov@collabora.com> Reviewed-by:
Bruce Cherniak <bruce.cherniak@intel.com> (cherry picked from commit e4a6ae06)
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In some APU situations the reported visible size can be larger than VRAM size. This properly clamps the value. Surprisingly both CTS and spec seem to allow a heap type with size 0, so this seemed like the easiest option to me. Signed-off-by:
Bas Nieuwenhuizen <basni@google.com> Fixes: 4ae84efb "radv: Use enum for memory heaps." Reviewed-by:
Dave Airlie <airlied@redhat.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Tested-by:
Michel Dänzer <michel.daenzer@amd.com> (cherry picked from commit 8229706a) [Emil Velikov: branch uses radeon_info::visible_vram_size] Signed-off-by:
Emil Velikov <emil.velikov@collabora.com> Conflicts: src/amd/vulkan/radv_device.c
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Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: "17.1 17.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 95c6a974)
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This implements a wait for glXWaitGL, glXCopySubBuffer, dri flush_front and creation of fake front until all pending SwapBuffers have been committed to hardware. Among other things this fixes piglit glx-copy-sub-buffers on dri3. Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by:
Brian Paul <brianp@vmware.com> Reviewed-by:
Sinclair Yeh <syeh@vmware.com> Reviewed-by:
Eric Anholt <eric@anholt.net> Cc: <mesa-stable@lists.freedesktop.org> (cherry picked from commit 185ef06f)
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The issue here is that the immediate is treated as a 64-bit value, and fetching it does not work reliably with swizzles that are different from xy and zw. Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit da83687c)
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Emil Velikov authored
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The optimizations are only valid for 32-bit integers. They were mistakenly firing for 64-bit integers as well. Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Matt Turner <mattst88@gmail.com> (cherry picked from commit de914615)
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Emil Velikov authored
Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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The resource struct is already allocated at this point and should be freed properly. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by:
Wladimir J. van der Laan <laanwj@gmail.com> (cherry picked from commit 4fb9f970)
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In the DRIImage queryImage hook, check if resource_get_handle() failed and return FALSE if so. Signed-off-by:
Daniel Stone <daniels@collabora.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit b4a18f13) [Emil Velikov: drop offset and modifier hunks - not in branch] Signed-off-by:
Emil Velikov <emil.velikov@collabora.com> Conflicts: src/gallium/state_trackers/dri/dri2.c
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On SI this was causing a hang in dEQP-VK.pipeline.render_to_image.core.2d_array.mipmap.r16g16_sint_s8_uint This was due to not handling the tile mode index for depth like I fixed previously for new GPUs. Fixes: 01d0c5a9 (radv: fix stencil regression since new addrlib import) Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit 800d1622) [Emil Velikov: XXX] Signed-off-by:
Emil Velikov <emil.velikov@collabora.com> Conflicts: src/amd/vulkan/radv_device.c
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This ports 72e46c98 to radv. radeonsi: apply a TC L1 write corruption workaround for SI Fixes: f4e499ec (radv: add initial non-conformant radv vulkan driver) Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit e77ff11f)
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This ports: da745366 radeonsi: don't apply the Z export bug workaround to Hainan to radv. Just noticed in passing. Fixes: f4e499ec (radv: add initial non-conformant radv vulkan driver) Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit a81e99f5)
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Fixes CTS dEQP-VK.memory.pipeline_barrier.host_write_uniform_texel_buffer.1024 on SI/CIK with radv. Fixes: f4e499ec (radv: add initial non-conformant radv vulkan driver) Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit ca82ef5a)
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If the layer base was > 0, it wasn't getting passed as the start instance or getting added in the shaders. Fixes CTS dEQP-VK.api.image_clearing.core.clear_color_attachment.2d_r8_uint_multiple_layers Fixes: 7e0382fb (radv: add support for layered clears (v2)) Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
Dave Airlie <airlied@redhat.com> (cherry picked from commit 75392e76)
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Emil Velikov authored
The last user of the function was removed with earlier commit. Fixes: 50842e8a ("swr: replace gallium->swr format enum conversion") Cc: Tim Rowley <timothy.o.rowley@intel.com> Signed-off-by:
Emil Velikov <emil.velikov@collabora.com> Reviewed-by:
Tim Rowley <timothy.o.rowley@intel.com> (cherry picked from commit a0755f2e)
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Emil Velikov authored
One can override the deviceID, by setting the INTEL_DEVID_OVERRIDE variable. A few symbolic names or a numerical value for the actual device ID is accepted. At the same time we're using strtod (string to double) to convert the string to a decimal numeral. A seeming thinko, made by the original commit that introduces the code in libdrm_intel and got here with the import. Fixes: 514db96c ("i965: Import libdrm_intel.") Signed-off-by:
Emil Velikov <emil.velikov@collabora.com> Reviewed-by:
Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 647b5a18)
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In the previous commit, forgot to apply v2 suggestions. Fixes: 28d0c38d (anv/pipeline: use unsigned long long constant to check enable vertex inputs) Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com> (cherry picked from commit 5cd4ece3)
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Emil Velikov authored
With ealier commit we relaxed the requirement from C++14 to C++11. Update the build script so that it Cc: Tim Rowley <timothy.o.rowley@intel.com Fixes: 0b80b025 ("swr: relax c++ requirement from c++14 to c++11") Signed-off-by:
Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 45927414)
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From KHR_fence_sync: When the condition of the sync object is satisfied by the fence command, the sync is signaled by the associated client API context, causing any eglClientWaitSyncKHR commands (see below) blocking on <sync> to unblock. The only condition currently supported is EGL_SYNC_PRIOR_COMMANDS_COMPLETE_KHR, which is satisfied by completion of the fence command corresponding to the sync object, and all preceding commands in the associated client API context's command stream. The sync object will not be signaled until all effects from these commands on the client API's internal and framebuffer state are fully realized. No other state is affected by execution of the fence command. If clients are passing the fence fd (from EGL_ANDROID_native_fence_sync) to a compositor, that fence must only be signaled once the framebuffer is resolved and not before as is currently the case. v2: fixup assert to use GL_SYNC_GPU_COMMANDS_COMPLETE (Chad) Reported-by:
Sergi Granell <xerpi.g.12@gmail.com> Fixes: c636284e ("i965/sync: Implement DRI2_Fence extension") Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Sergi Granell <xerpi.g.12@gmail.com> Cc: Rob Clark <robdclark@gmail.com> Cc: Chad Versace <chadversary@chromium.org> Cc: Daniel Stone <daniels@collabora.com> Cc: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by:
Chad Versace <chadversary@chromium.org> (cherry picked from commit 618be8cc)
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Emil Velikov authored
The commit addresses an earlier fix, which did not land in branch. Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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Emil Velikov authored
Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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Emil Velikov authored
Addresses commit which did not land in branch. Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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Emil Velikov authored
The bindless work did not land in branch. Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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Emil Velikov authored
Applied to master and reverted shortly afterwords. Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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Emil Velikov authored
They depend on the merged shaders (re)work which landed past the 17.1 branchpoint. Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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Emil Velikov authored
Explicit 17.2 nomination, since it depends on refactoring past the 17.1 branchpoint. Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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Emil Velikov authored
Addresses commit merged past the 17.1 brancpoint. Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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Emil Velikov authored
Both are explicit 17.2 nominations, since they depend on work which landed past the 17.1 branchpoint. Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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This fixes a bug uncovered by: 2412c4c8 util: Make CLAMP turn NaN into MIN. Cc: 17.2 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit 433f6f7a)
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The number of supported waves per thread group has been reduced to 16 with gfx9. Trying to use 32 waves causes hangs, and barriers might not work correctly with > 16 waves. Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit a0e6b9a2) [Emil Velikov: add a HAVE_LLVM check, as applicable in branch] Signed-off-by:
Emil Velikov <emil.velikov@collabora.com> Conflicts: src/gallium/drivers/radeon/r600_pipe_common.c
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The firmware version numbers for SI were wrong. The new numbers are probably too conservative (we don't have a definitive answer by the firmware team), but DRAW_INDIRECT_MULTI has been confirmed to work with these versions on Tahiti (by Gustaw) and on Verde (by myself). While this is technically adding a feature, it's a feature we thought we had for a long time. The change is small enough and we're early enough in the 17.2 release cycle that it should still go in. Reported-by:
Gustaw Smolarczyk <wielkiegie@gmail.com> Cc: 17.2 <mesa-stable@lists.freedesktop.org> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 65fbaab0)
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The EU limit of 128 GRFs should allow 32 vertex elements of 4 GRFs. However, the maximum allowed value of "Vertex URB Entry Read Length" in SIMD8 is 15. And 15 * 8 = 120 gives us a limit of 30 vertex elements. Because we also need to reserve a vertex buffer to upload VertexIndex/InstanceIndex and another to upload DrawID when needed, we can only expose 28. Cc: "17.2" <mesa-stable@lists.freedesktop.org> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 31f1863a)
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Cc: "17.2" <mesa-stable@lists.freedesktop.org> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit a848e693)
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Emil Velikov authored
Addesses 0f9b609c, which landed shortly before the 17.2 branchpoint. Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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Emil Velikov authored
Addesses 63a43f41, which landed shortly before the 17.2 branchpoint. Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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As Chris commented, it makes more sense to have batch buffer flushes before the query. Usually applications like frame_retrace do a series of queries and in that case, with flushes at the end of the queries, we might still have the first query contained in 2 different batchs. More generally it would be quite usual to have the query contained in 2 batch buffers because we never now what's the fill rate of the current batch buffer. If we move the flushing at the beginning of the queries, it's pretty much guaranteed that queries will be contained in a single batch buffer (unless the amount of commands is huge, but then it's only fair to include reloading request times in the measurements). Fixes: adafe4b7 ("i965: perf: minimize the chances to spread queries across batchbuffers") Reported-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: "17.2 17.1" <mesa-stable@lists.freedesktop.org> Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 9f439ae1)
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I don't know how I managed to leave this here for so long. Found when working on a 1:1 overlapping blit extension for X11. Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 93fec49a)
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