- May 17, 2023
-
-
Signed-off-by:
Rohan Garg <rohan.garg@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!23075>
-
Signed-off-by:
Rohan Garg <rohan.garg@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!23075>
-
affects: GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_linear_filter_color_blit cc: mesa-stable Reviewed-by:
Joshua Ashton <joshua@froggi.es> Part-of: <mesa/mesa!22959>
-
this is needed by some apps cc: mesa-stable Reviewed-by:
Joshua Ashton <joshua@froggi.es> Part-of: <mesa/mesa!22959>
-
Signed-off-by:
James Glanville <james.glanville@imgtec.com> Reviewed-by:
Frank Binns <frank.binns@imgtec.com> Part-of: <mesa/mesa!22958>
-
Fixes: dEQP-VK.renderpass.suballocation.formats.r16g16_sint.input .dont_care.dont_care.self_dep_clear Signed-off-by:
James Glanville <james.glanville@imgtec.com> Reviewed-by:
Frank Binns <frank.binns@imgtec.com> Part-of: <!22958>
-
In copy to buffer region, set dest rect to region size. The rectangle must be block size adjusted in case of block compressed format. Fix test: dEQP-VK.api.copy_and_blit.core.image_to_buffer.regions Signed-off-by:
Oskar Rundgren <oskar.rundgren@imgtec.com> Reviewed-by:
Frank Binns <frank.binns@imgtec.com> Part-of: <!22958>
-
The transfer command "struct pvr_transfer_cmd" has support for features not used by Vulkan: colour key, pattern, rop blit and alpha blending The whole "struct pvr_transfer_blit" can be removed. Also all code related to transfer alpha blending can be removed. This is an optimisation and doesn't fix any dEQP tests. Signed-off-by:
Oskar Rundgren <oskar.rundgren@imgtec.com> Reviewed-by:
Frank Binns <frank.binns@imgtec.com> Part-of: <mesa/mesa!22958>
-
The mask should be inverted. Fixes tests in dEQP-VK.api.copy_and_blit.* using the texel unwind workaround. Signed-off-by:
Oskar Rundgren <oskar.rundgren@imgtec.com> Reviewed-by:
Frank Binns <frank.binns@imgtec.com> Part-of: <!22958>
-
Fix the rectangle mappings used with texel unwind workaround (unaligned address). Signed-off-by:
Oskar Rundgren <oskar.rundgren@imgtec.com> Reviewed-by:
Frank Binns <frank.binns@imgtec.com> Part-of: <!22958>
-
The byte unwind workaround can be used when source texture virtual address doesn't meet HW requirements (is unaligned) and the pixel format can't be changed i.e. destination is compressed. If destination texture is not compressed the simpler texel extend workaround can be used. Currently byte unwind workaround has bugs so removing the workaround fixes tests in dEQP-VK.api.copy_and_blit.core.blit_image.simple_tests.* when they instead use texel extend workaround. Signed-off-by:
Oskar Rundgren <oskar.rundgren@imgtec.com> Reviewed-by:
Frank Binns <frank.binns@imgtec.com> Part-of: <!22958>
-
The rectangles in "struct pvr_rect_mapping" are unsigned so a flipped rectangle mapping isn't possible. Add new struct members flip_x and flip_y to specify flipped mapping. Add support for flipped rectangles in transfer copy blit path. Support for flipped rectangles in the clip blit path is not done in this change. The new booleans are false by default because transfer command "struct pvr_transfer_cmd" is zeroed on allocation in pvr_transfer_cmd_alloc (pvr_blit.c). Fixes: dEQP test case: dEQP-VK.api.copy_and_blit.core.blit_image.simple_tests .mirror_xy.nearest Signed-off-by:
Oskar Rundgren <oskar.rundgren@imgtec.com> Reviewed-by:
Frank Binns <frank.binns@imgtec.com> Part-of: <!22958>
-
Block compressed formats with 3d twiddled memory layout not supported. Signed-off-by:
Oskar Rundgren <oskar.rundgren@imgtec.com> Reviewed-by:
Frank Binns <frank.binns@imgtec.com> Part-of: <!22958>
-
Twiddled surfaces don't use stride but printing info about ignored stride is not useful on debug driver. Signed-off-by:
Oskar Rundgren <oskar.rundgren@imgtec.com> Reviewed-by:
Frank Binns <frank.binns@imgtec.com> Part-of: <!22958>
-
The swizzle of pipe formats is described in "struct util_format_description". The struct has array "unsigned char swizzle[4];". The index of the array is the colour channel (in the order R, G, B and A). The value is what position the colour channel is sourced from. In PBE register settings (REG_SWIZ_CHAN[0-3]) the register index is output channel position (and not colour). The colours are in the PBE source channels - SWIZ_SOURCE_CHAN0 typically red. The function pvr_get_pbe_hw_swizzle doesn't translate the swizzle correctly. Remove function and replace with switch for each colour. This could be done in a for loop, but there is just as much code in the loop, it involves pointers and it's less readable for humans. That's why I opted for this implementation. Fixed test: dEQP-VK.api.copy_and_blit.core.image_to_image .all_formats.color.2d.r4g4b4a4_unorm_pack16.b4g4r4a4_unorm_pack16 and other with this pixel format. Signed-off-by:
Oskar Rundgren <oskar.rundgren@imgtec.com> Reviewed-by:
Frank Binns <frank.binns@imgtec.com> Part-of: <!22958>
-
Otherwise the VRS state isn't reset and the graphics pipeline might still use the previous VRS state. The VRS state will only be re-emitted if it's different when the pipeline is bound. Closes: mesa/mesa#9005 Cc: mesa-stable Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!23052>
-
Pierre-Eric Pelloux-Prayer authored
This fixes building with recent LLVM where these 2 .h files were removed. Closes: mesa/mesa#8671 Acked-By:
Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!22980>
-
Found this while debugging a VRS issue with Valhalla. Fixes: 87245c6e ("radv: handle NULL fragment shaders when recording cmdbuf") Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!23050>
-
This was horror I should have cleaned up before, clean it up before mesh shaders make it worse. Reviewed-by:
Brian Paul <brianp@vmware.com> Part-of: <!22788>
-
Reviewed-by:
Brian Paul <brianp@vmware.com> Part-of: <!22788>
-
This leaves the cache stuff in place, but we should consider trying to consolidate that. Reviewed-by:
Brian Paul <brianp@vmware.com> Part-of: <!22788>
-
Now that the other code is consoldiated it makes sense to just consolidate this binding code between the drivers and core Reviewed-by:
Brian Paul <brianp@vmware.com> Part-of: <!22788>
-
These can all be the same now. Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Reviewed-by:
Brian Paul <brianp@vmware.com> Part-of: <!22788>
-
Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Reviewed-by:
Brian Paul <brianp@vmware.com> Part-of: <!22788>
-
This lines them up just like the draw ones. Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Reviewed-by:
Brian Paul <brianp@vmware.com> Part-of: <!22788>
-
this makes all the structs have the same baseline members for resources and aniso_filter_table. Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Reviewed-by:
Brian Paul <brianp@vmware.com> Part-of: <mesa/mesa!22788>
-
Part-of: <!21593>
-
Part-of: <!21593>
-
- May 16, 2023
-
-
The intrinsics are now totally dead and can be removed. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <!23036>
-
Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!23036>
-
NEW_ATOMIC isn't so new anymore. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!23036>
-
We duplicated the validation for unified vs legacy atomics, so drop the unused latter set. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!23036>
-
Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!23036>
-
Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!23036>
-
This commit drops legacy atomic support from core passes where we can simply delete switch cases with no other changes. As such it's separated from the more complex pass-specific commits for ease of review. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!23036>
-
Not seen. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!23036>
-
No more users. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <!23036>
-
There are no more producers of legacy atomics so these calls are inert. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <!23036>
-
Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!23036>
-
Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!23036>
-