- Nov 18, 2014
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Emil Velikov authored
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
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DRI_PRIME setups have different issues due the lack of dma-buf fences support in the drivers. For DRI3 DRI_PRIME, a race can appear, making tearings visible, or worse showing older content than expected. Until dma-buf fences are well supported (and by all drivers), an alternative is to send the buffers to the server only when rendering has finished. Since waiting the rendering has finished in the main thread has a performance impact, this patch uses an additional thread to offload the wait and the sending of the buffers to the server. Acked-by: Jose Fonseca <jfonseca@vmware.com> Reviewed-by: David Heidelberg <david@ixit.cz> Signed-off-by: Axel Davy <axel.davy@ens.fr> (cherry picked from commit 7f565845)
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Implements vblank_mode and throttling, which allows us change default ratio between framerate and input lag. Acked-by: Jose Fonseca <jfonseca@vmware.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Axel Davy <axel.davy@ens.fr> (cherry picked from commit 948e6c52)
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Work of Joakim Sindholt (zhasha) and Christoph Bumiller (chrisbmr). DRI3 port done by Axel Davy (mannerov). v2: - nine_debug.c: klass extended from 32 chars to 96 (for sure) by glennk - Nine improvements by Axel Davy (which also fixed some wine tests) - by Emil Velikov: - convert to static/shared drivers - Sort and cleanup the includes - Use AM_CPPFLAGS for the defines - Add the linker garbage collector - Restrict the exported symbols (think llvm) v3: - small nine fixes - build system improvements by Emil Velikov v4: [Emil Velikov] - Do no link against libudev. No longer needed. Acked-by: Jose Fonseca <jfonseca@vmware.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Axel Davy <axel.davy@ens.fr> Signed-off-by: David Heidelberg <david@ixit.cz> (cherry picked from commit fdd96578) [Emil Velikov: use correct ureg_property* functions] Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
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v3: thanks to Brian, improved coding style, also glennk helped spot few things (unsigned -> int, two constify) v4: thanks Ilia improved function, dropped u_box_clip_3d v5: incorporated rest of Gregor proposed changes,clean ups v6: u_box_clip_2d simplify proposed by Ilia Mirkin Acked-by: Jose Fonseca <jfonseca@vmware.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: David Heidelberg <david@ixit.cz> (cherry picked from commit 7d2573b5)
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At this moment we use only zero or positive values. v2: Implement it for also for Solaris, MSVC assembly and enable for other combinations. v3: Replace MSVC assembly by assert + warning during compilation v4: remove inc and dec with return for MSVC assembly Acked-by: Jose Fonseca <jfonseca@vmware.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: David Heidelberg <david@ixit.cz> (cherry picked from commit cb491321)
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Implement pipe_loader_sw_probe_wrapped which allows to use the wrapped software renderer backend when using the pipe loader. v2: - remove unneeded ifdef - use GALLIUM_PIPE_LOADER_WINSYS_LIBS - check for CALLOC_STRUCT thanks to Emil Velikov Acked-by: Jose Fonseca <jfonseca@vmware.com> Signed-off-by: David Heidelberg <david@ixit.cz> (cherry picked from commit e23d63cf)
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Acked-by: Jose Fonseca <jfonseca@vmware.com> Signed-off-by: David Heidelberg <david@ixit.cz> (cherry picked from commit 8314315d)
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v2: moved in in same order as in p_shader_tokens (thanks Brian) Acked-by: Jose Fonseca <jfonseca@vmware.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: David Heidelberg <david@ixit.cz> (cherry picked from commit 259ec77d)
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- Nov 15, 2014
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This will be reused for the scalar VS pass. v2 (Ken): Rebase on master. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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We'll reuse this toplevel optimization driver for the scalar VS. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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These last few operations all only apply when we've actually generated code, optimized and allocated registers. The dummy and the repclear shaders don't need the gen4 send workaround, and don't spill. This means we can move these lines into the else-branch, which will make the following refactoring easier. v2 (Ken): Rebase on master, which removed the uncompressed stack. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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We split out SIMD8 and SIMD16 generation into seperate calls to new method generate_code(), which returns the start offset for the generated code. A new get_assembly() method returns the generated code. This avoids asserting MESA_SHADER_FRAGMENT and accessing wm_prog_data in the generator. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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- Nov 14, 2014
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Jose Fonseca authored
Derived from st/glx's GLX_EXT_create_context_es/es2_profile implementation. Tested with an OpenGL ES 2.0 ApiTrace. Reviewed-by: Brian Paul <brianp@vmware.com>
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Jose Fonseca authored
Tested with piglit glx tests. Reviewed-by: Brian Paul <brianp@vmware.com>
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Rob Clark authored
Split out a few helpers from fd3_program so we don't have to duplicate for fd4_program. Signed-off-by: Rob Clark <robclark@freedesktop.org>
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Rob Clark authored
Gets rid of a namespace conflict w/ a4xx which wants an fd4_draw() version of fd_draw().. Signed-off-by: Rob Clark <robclark@freedesktop.org>
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Rob Clark authored
Signed-off-by: Rob Clark <robclark@freedesktop.org>
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Rob Clark authored
Signed-off-by: Rob Clark <robclark@freedesktop.org>
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Rob Clark authored
Handle hrN.c in printing outputs/inputs. Signed-off-by: Rob Clark <robclark@freedesktop.org>
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Jose Fonseca authored
The latest version of the specs explicitly allow it, and given that Mesa universally supports KHR_debug we should definitely support it. Totally untested. (Just happened to noticed this while implementing GLX_EXT_create_context_es2_profile for st/xlib.) Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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Marek Olšák authored
Acked-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Eric Anholt <eric@anholt.net> Informally acked-by: Jose Fonseca
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Marek Olšák authored
Acked-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Eric Anholt <eric@anholt.net> Informally acked-by: Jose Fonseca
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Kenneth Graunke authored
17 insertions(+), 102 deletions(-). Works just as well. v2: Make emit_math take const references (suggested by Matt), drop redundant WRITEMASK_XYZW setting (Matt and Curro). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
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Kenneth Graunke authored
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
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Kenneth Graunke authored
We do this almost everywhere else; this should make it easier to modify. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
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- Nov 13, 2014
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Ben Widawsky authored
Every other unit in the geometry pipeline automatically enables statistics gathering. This part of the pipe has been controlled by the DEBUG_STATS variable, but this is asymmetric. This dates back to the original implementation, and I am not sure if there is a reason for it. I need access to these stats to implement ARB_pipeline_statistics_query. Eric wrote it, and Ken touched it last. Do you have any opposition? Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86145 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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Ville Syrjälä authored
According to gen2 BSpec the pipeline must be flushed at least up to the windower before changing the scissor rect enable field. Emitting the 3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE is sufficient to do that. gen3 BSpec no longer has that piece of text, but let's make the same change there too for symmetry. The spec does still say that the scissor rectangle must be defined before enabling it, so the new order does seem more in line with the spec. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Ville Syrjälä authored
Gen2 doesn't have fragment shaders so we shouldn't be calling _mesa_meta_glsl_Clear() on gen2. Restore the appropriate ARB_fragment_shader check to the clear path which was lost in: commit 94f22fbe Author: Tapani Pälli <tapani.palli@intel.com> Date: Wed Aug 8 20:46:45 2012 +0300 intel: use _mesa_meta_Clear with OpenGL ES 1.1 v2 v2: Fix spelling in commit message Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Ville Syrjälä authored
TEXTURE_SET() is the only register macro that forgets to wrap the argument evaluation in parens. Only simple integers are passed to this macro so there's no bug but sitll it seems prudent to add the parens. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Ville Syrjälä authored
ctx.hw_stencil is not used anywhere so kill it. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Ville Syrjälä authored
Gen2 doesn't support depth/stencil textures, and since commit c1d4d499 Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Thu Apr 24 14:11:43 2014 +0300 i915: Don't advertise Z formats in TextureFormatSupported on gen2 depth/stencil formats are no longer accepted as texture formats. However we still want depth/stencil renderbuffers, so add explicit format checks to intel_alloc_renderbuffer_storage() to allow such things. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Ville Syrjälä authored
gen2 doesn't supporte linear mip filter with anisotropic min/mag filtering. The hardware would automagically downgrade the min/mag filters to linear in such cases, which IMO looks worse than forcing the mip filter to nearest. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Ville Syrjälä authored
Gen2 doesn't support the A8 texture format. Currently the driver substitutes it with I8, but that results in incorrect RGB values. Use A8L8 instead. We end up wasting a bit of memory, but at least we should get the correct results. v2: Handle the fallback in _mesa_choose_tex_format() and also do it for all alpha formats that currently accept A8 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72819 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80050 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38873 Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Ville Syrjälä authored
The spec says using DOT4 for alpha is undefined unless DOT4 is also used for color. It seems to do the right thing anyway, but better safe than sorry. Also override numAlphaArgs to 2 for DOT4 since that's what it wants. This migth fix something in case the specified alpha mode has only one argument. Also avoids emitting a needless 3DSTATE_MAP_BLEND_ARG if the specified alpha mode has three arguments. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Neil Roberts authored
Reviewed-by: Brian Paul <brianp@vmware.com>
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Jose Fonseca authored
To address http://lists.freedesktop.org/archives/mesa-dev/2014-November/070569.html In short, revert 706ad3b6 for non-Windows OSes.
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Kenneth Graunke authored
See 546d6c8d for the corresponding fix in freedreno. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Stephane Marchesin <stephane.marchesin@gmail.com> Cc: "10.3" <mesa-stable@lists.freedesktop.org>
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Emma Anholt authored
add_output() can resize the qreg array, so we might use a stale pointer.
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Emma Anholt authored
All the shaders we've received so far had this be the case, but with nir-to-tgsi that changed. I might decide to make nir-to-tgsi keep the outputs in the same order, for debugging sanity, but I'm not sure.
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