radeonsi: completely rework updating descriptors without CP DMA
The patch has a better explanation. Just a summary here:
- The CPU always uploads a whole descriptor array to previously-unused memory.
- CP DMA isn't used.
- No caches need to be flushed.
- All descriptors are always up-to-date in memory even after a hang, because
CP DMA doesn't serve as a middle man to update them.
This should bring:
- better hang recovery (descriptors are always up-to-date)
- better GPU performance (no KCACHE and TC flushes)
- worse CPU performance for partial updates (only whole arrays are uploaded)
- less used IB space (no CP_DMA and WRITE_DATA packets)
- simpler code
- hopefully, some of the corruption issues with SI cards will go away.
If not, we'll know the issue is not here.
Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com>
- src/gallium/drivers/radeonsi/si_descriptors.c 116 additions, 238 deletionssrc/gallium/drivers/radeonsi/si_descriptors.c
- src/gallium/drivers/radeonsi/si_pipe.h 0 additions, 6 deletionssrc/gallium/drivers/radeonsi/si_pipe.h
- src/gallium/drivers/radeonsi/si_state.h 10 additions, 22 deletionssrc/gallium/drivers/radeonsi/si_state.h
- src/gallium/drivers/radeonsi/si_state_draw.c 2 additions, 5 deletionssrc/gallium/drivers/radeonsi/si_state_draw.c