nir: Introduce new nir_intrinsic_load_per_vertex_input intrinsics.
Geometry and tessellation shaders process multiple vertices; their inputs are arrays indexed by the vertex number. While GLSL makes this look like a normal array, it can be very different behind the scenes. On Intel hardware, all inputs for a particular vertex are stored together - as if they were grouped into a single struct. This means that consecutive elements of these top-level arrays are not contiguous. In fact, they may sometimes be in completely disjoint memory segments. NIR's existing load_input intrinsics are awkward for this case, as they distill everything down to a single offset. We'd much rather keep the vertex ID separate, but build up an offset as normal beyond that. This patch introduces new nir_intrinsic_load_per_vertex_input intrinsics to handle this case. They work like ordinary load_input intrinsics, but have an extra source (src[0]) which represents the outermost array index. v2: Rebase on earlier refactors. v3: Use ssa defs instead of nir_srcs, rebase on earlier refactors. Signed-off-by:Kenneth Graunke <kenneth@whitecape.org> Reviewed-by:
Jason Ekstrand <jason.ekstrand@intel.com>
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- src/glsl/nir/nir_intrinsics.h 1 addition, 0 deletionssrc/glsl/nir/nir_intrinsics.h
- src/glsl/nir/nir_lower_io.c 49 additions, 6 deletionssrc/glsl/nir/nir_lower_io.c
- src/glsl/nir/nir_print.c 2 additions, 0 deletionssrc/glsl/nir/nir_print.c
- src/mesa/drivers/dri/i965/brw_nir.c 11 additions, 2 deletionssrc/mesa/drivers/dri/i965/brw_nir.c
- src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp 23 additions, 35 deletionssrc/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
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