- Mar 01, 2014
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Ian Romanick authored
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
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Emil Velikov authored
The variable name states megabytes, while we calculate the amount in kilobytes. Correct this by dividing with the correct amount. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Cc: "10.0 10.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (cherry picked from commit fc25956b)
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Brian Paul authored
Fixes glGetTexImage() when converting from MESA_FORMAT_Z32_FLOAT_S8X24_UINT to GL_UNSIGNED_INT_24_8. Hit by the piglit ext_packed_depth_stencil-getteximage test. Cc: "10.0" "10.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit a12d4d03)
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- Feb 28, 2014
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Ian Romanick authored
Though it won't matter on Linux, use _mesa_align_free to release it. Since i965 doesn't have sys_buffer, I overlooked this in the GL_ARB_map_buffer_alignment work a few months ago. Fixes i915 (and presumably i830) regressions in ARB_map_buffer_range tests and the failure in arb_map_buffer_alignment-sanity_test. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74960 Cc: "10.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit ff2cbf9e)
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Ian Romanick authored
There's no reason to have more vertex texture units than fragment texture units on this hardware. Since increasing the default maximum number of texture units from 16 to 32, this has triggered some segfault in i915 driver. There's probably some array or bitfield that isn't properly sized now. This really papers over the bug, but I don't think I'll lose any sleep over that. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74071 Cc: "10.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit 8ba15700)
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Petri Latvala authored
v2: Don't add function parameters, pass the required size in prog_data->nr_params. v3: - Use the name uniform_array_size instead of uniform_param_count. - Round up when dividing param_count by 4. - Use MAX2() instead of taking the maximum by hand. - Don't crash if prog_data passed to vec4_visitor constructor is NULL v4: Rebase for current master v5 (idr): Trivial whitespace change. Signed-off-by: Petri Latvala <petri.latvala@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71254 Cc: "10.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (cherry picked from commit 7189fce2)
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Tom Stellard authored
This prevents clover from using unsupported devices. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> CC: "10.0 10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit f61e382f)
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Matt Turner authored
Cc: "10.1" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75224 (cherry picked from commit 4bd7f1d0)
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Matt Turner authored
Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 5eff8576)
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Brian Paul authored
glGetTexImage(GL_DEPTH_STENCIL, GL_UNSIGNED_INT_24_8) was just using memcpy() instead of _mesa_unpack_uint_24_8_depth_stencil_row() to convert texels from the hardware format to the GL format. Fixes issue reported by David Meng at Intel. The new piglit ext_packed_depth_stencil-getteximage test checks for this bug. Also, add some format/type assertions. We don't yet handle the GL_FLOAT_32_UNSIGNED_INT_24_8_REV type. That should be fixed in a follow-on patch. Reviewed-by: Eric Anholt <eric@anholt.net> Cc: "10.0" "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 43dee029)
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Thomas Hellstrom authored
This avoids the kernel driver spewing out errors about the param not being supported. Also correct the max surface size used when the kernel does not support the query. Reported-by: Brian Paul <brianp@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit f5e681f3)
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- Feb 27, 2014
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Anuj Phogat authored
intelEmitCopyBlit uses a signed 16-bit integer to represent buffer pitch, so it can only handle buffer pitches < 32k. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (cherry picked from commit b3094d99)
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Kenneth Graunke authored
sh->Source is NULL and this will segfault. Fixes MESA_GLSL=dump with "The Swapper". Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit f896e823)
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Kenneth Graunke authored
Tt's kind of a trap---calling do_common_optimization() after lower_instructions() may cause opt_algebraic() to reintroduce ir_triop_lrp expressions that were lowered, effectively defeating the point. Because of this, nobody uses it. v2: Delete more code (caught by Ian Romanick). Cc: "10.1" <mesa-stable@lists.freedesktop.org> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Acked-by: Eric Anholt <eric@anholt.net> (cherry picked from commit ac0a8b95)
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Kenneth Graunke authored
Both the vector and scalar backends now support it natively, so there's no point in lowering it. Cc: "10.1" <mesa-stable@lists.freedesktop.org> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Acked-by: Eric Anholt <eric@anholt.net> (cherry picked from commit 2fdea48e)
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Kenneth Graunke authored
When the vec4 backend encountered an ir_triop_lrp, it always emitted an actual LRP instruction, which only exists on Gen6+. Gen4-5 used lower_instructions() to decompose ir_triop_lrp at the IR level. Since commit 8d37e991 ("glsl: Optimize open-coded lrp into lrp."), we've had an bug where lower_instructions translates ir_triop_lrp into arithmetic, but opt_algebraic reassembles it back into a lrp. To avoid this ordering concern, just handle ir_triop_lrp in the backend. The FS backend already does this, so we may as well do likewise. v2: Add a comment reminding us that we could emit better assembly if we implemented the infrastructure necessary to support using MAC. (Assembly code provided by Eric Anholt). Cc: "10.1" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75253 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Acked-by: Eric Anholt <eric@anholt.net> (cherry picked from commit 56879a7a)
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Kenneth Graunke authored
Three source instructions didn't exist until Gen6. vec4_generator has assertions to catch this, but catching it in the visitor provides a nicer backtrace. Cc: "10.1" <mesa-stable@lists.freedesktop.org> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Acked-by: Eric Anholt <eric@anholt.net> (cherry picked from commit ffde483f)
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Francisco Jerez authored
Reviewed-by: Paul Berry <stereotype441@gmail.com> (cherry picked from commit 98306e72)
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- Feb 26, 2014
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Brian Paul authored
Requested by Marek. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit e4a5a9fd)
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The linux winsys needs to know whether a surface is shared. For guest-backed surfaces we need this information to avoid allocating a mob out of the mob cache for shared surfaces, but instead allocate a shared mob, that is never put in the mob cache, from the kernel. Also previously, all surfaces were given the "shareable" attribute when allocated from the kernel. This is too permissive for client-local surfaces. Now that we have the needed info, only set the "shareable" attribute if the client indicates that it needs to share the surface. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Jakob Bornecrantz <jakob@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 141e39a8)
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Brian Paul authored
This is a squash commit of many commits by Thomas Hellstrom. Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit fe6a8544)
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Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 59e7c596)
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In some situations, it may be desirable to bypass the cache at buffer creation but to insert the buffer in the cache at buffer destruction. One such situation is where we already have a kernel representation of a buffer that we want to use, but we also want to insert it in the cache when it's freed up. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: José Fonseca <jfonseca@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 8af358d8)
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In some situations it's important to restrict the sizes of buffers that the cached buffer manager is allowed to return Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit c9e9b186)
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Brian Paul authored
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 3d1fd6df)
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Brian Paul authored
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 72b0e959)
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Brian Paul authored
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit e0a6fb09)
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Brian Paul authored
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 6476bcbc)
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Brian Paul authored
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit f8bbd826)
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Brian Paul authored
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit d0c22a6d)
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Brian Paul authored
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit c1e60a61)
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Brian Paul authored
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit f84c830b)
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Brian Paul authored
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 2f1fc8db)
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Brian Paul authored
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 31dfefc4)
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Brian Paul authored
And update some existing commands. Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 823fbfdc)
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Brian Paul authored
This adds new interface functions for guest-backed surfaces and adds a mobid parameter to the surface_relocation() function. Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit d993ada5)
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Brian Paul authored
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 02471138)
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Brian Paul authored
The old svga3d_reg.h file is split into separate header files and we add new items for guest-backed surfaces. Plus some minor code fixes because of renamed symbols. Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: "10.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 2e0c9084)
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Brian Paul authored
Signed-off-by: Brian Paul <brianp@vmware.com> (cherry picked from commit 23d4ff53)
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Brian Paul authored
If the shader is too large, plug in a dummy shader. This patch also reworks the existing dummy shader code. Reviewed-by: Jose Fonseca <jfonseca@vmware.com> (cherry picked from commit 97fdace6)
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