- Aug 15, 2018
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Andres Gomez authored
Signed-off-by: Andres Gomez <agomez@igalia.com>
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- Aug 14, 2018
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Follow radeonsi. Fixes: 3665f66e "radv: Add support for ETC2 textures." Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 4bb6c493)
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Behavior wrt firstInstance got changed, and a divisor of 0 has been disallowed. The new version of the ext got published in specification 1.1.81. Sending to stable since the only known user is DXVK, which needs this for correctness. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> CC: 18.2 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 66e12451)
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CC: <mesa-stable@lists.freedesktop.org> Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit bf33ca75)
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- Aug 13, 2018
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One of the reasons we didn't notice that R24_UNORM_X8_TYPELESS destinations were broken was that an earlier layer was swapping it out for B8G8R8A8_UNORM. That made Z24X8 -> Z24X8 blits work. However, R32_FLOAT -> R24_UNORM_X8_TYPELESS was still totally broken. The old code only considered one format at a time, without thinking that format conversion may need to occur. This patch moves the translation out to a place where it can consider both formats. If both are Z24X8, we continue using B8G8R8A8_UNORM to avoid having to do shader math workarounds. If we have a Z24X8 destination, but a non-matching source, we use our shader hacks to actually render to it properly. Fixes: 804856fa (intel/blorp: Handle more exotic destination formats) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit de57926d)
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The hardware doesn't support rendering to R24_UNORM_X8_TYPELESS, so Jason decided to fake it with a bit of shader math and R32_UNORM RTs. The only problem is that R32_UNORM isn't renderable either...so we've just traded one bad format for another. This patch makes us use R32_UINT instead. Fixes: 804856fa (intel/blorp: Handle more exotic destination formats) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 8a290862)
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The Vulkan 1.1.82 spec flipped the order to better match D3D. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> (cherry picked from commit a9f7bcfd)
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- Aug 10, 2018
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The check for ETC2 compatibility was not updated when the fallback format was changed. Fixes: 71867a0a st/mesa: Fall back to R8G8B8A8_SRGB for ETC2 Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit e94095ec)
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This is basically copied from the DRI2 destroy path. Without this, Raspberry Pi would quickly run out of CMA during the EGL tests in the CTS due to all the pixmaps laying around. Fixes: f35198ba ("egl/x11: Implement dri3 support with loader's dri3 helper") Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit b618d7ea)
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When the SIMD16 Gen4-5 fragment shader payload contains source depth (g2-3), destination stencil (g4), and destination depth (g5-6), the single register of stencil makes the destination depth unaligned. We were generating this instruction in the RT write payload setup: mov(16) m14<1>F g5<8,8,1>F { align1 compr }; which is illegal, instructions with a source region spanning more than one register need to be aligned to even registers. This is because the hardware implicitly does (nr | 1) instead of (nr + 1) when splitting the compressed instruction into two mov(8)'s. I believe this would cause the hardware to load g5 twice, replicating subspan 0-1's destination depth to subspan 2-3. This showed up as 2x2 artifact blocks in both TIS-100 and Reicast. Normally, we rely on the register allocator to even-align our virtual GRFs. But we don't control the payload, so we need to lower SIMD widths to make it work. To fix this, we teach lower_simd_width about the restriction, and then call it again after lower_load_payload (which is what generates the offending MOV). Fixes: 8aee87fe (i965: Use SIMD16 instead of SIMD8 on Gen4 when possible.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107212 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=13728 Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Tested-by: Diego Viola <diego.viola@gmail.com> (cherry picked from commit 08a5c395)
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This extension is not defined for indirect contexts. Marking it as "client only", as the old code did here, would make the extension available in indirect contexts, even though the server would certainly not have it in its extension list. Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Adam Jackson <ajax@redhat.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 63a6b719)
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Return ir_rvalue::error_value with ast_post_inc, ast_post_dec if parser error was emitted previously. This way process_array_size won't see bogus IR generated like with commit 9c676a64. Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98699 Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (cherry picked from commit 03a5acec)
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This fixes both Metro 2033 Redux and Metro Last Light Redux Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99730 Signed-off-by: Eero Tamminen <eero.t.tamminen@intel.com> Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (cherry picked from commit e0de26ea)
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- Aug 09, 2018
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Fixes: 6a60beba "intel/tools: Add an error state to aub translator" Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit aac80f75)
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We won't have an FD if we're just having the server wait on a fence created by eglCreateSyncKHR(). Our seqno fences will happen in order, so server-side waits are no-ops in that case. Fixes dEQP-EGL.functional.sharing.gles2.multithread.simple_egl_server_sync.buffers.gen_delete Fixes: b0acc3a5 ("broadcom/vc4: Native fence fd support") (cherry picked from commit cfe69d0a)
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With earlier rework the user and provider of the symbol are within the same binary. Thus there's no point in exporting the function. Spotted while reviewing patch from Chuck, that nearly added another unneeded PUBLIC function. Cc: Chuck Atkins <chuck.atkins@kitware.com> Cc: Tim Rowley <timothy.o.rowley@intel.com> Fixes: f50aa214 "(swr: build driver proper separate from rasterizer") Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Tested-by: Chuck Atkins <chuck.atkins@kitware.com> Reviewed-By: George Kyriazis <george.kyriazis@intel.com<mailto:george.kyriazis@intel.com>> Tested-by: Chuck Atkins <chuck.atkins@kitware.com<mailto:chuck.atkins@kitware.com>> (cherry picked from commit 54d84489)
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According to EGL 1.5 spec, section 3.10.1.1 ("Native Window Resizing"): "If the native window corresponding to _surface_ has been resized prior to the swap, _surface_ must be resized to match. _surface_ will normally be resized by the EGL implementation at the time the native window is resized. If the implementation cannot do this transparently to the client, then *eglSwapBuffers* must detect the change and resize surface prior to copying its pixels to the native window." So far, resizing a native window in Wayland/EGL was interpreted in Mesa as a request to resize, which is not executed until the first draw call. And hence, surface size is not updated until executing it. Thus, querying the surface size with eglQuerySurface() after a window resize still returns the old values. This commit updates the surface size values as soon as the resize is done, even when the real resize is done in the draw call. This makes the semantics that any native window resize request take effect inmediately, and if user calls eglQuerySurface() it will return the new resized values. v2: update surface size if there isn't a back surface (Daniel) CC: Daniel Stone <daniel@fooishbar.org> CC: mesa-stable@lists.freedesktop.org Reviewed-by: Daniel Stone <daniels@collabora.com> (cherry picked from commit a9fb331e)
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When creating a windows surface with eglCreateWindowSurface(), the width and height returned by eglQuerySurface(EGL_{WIDTH,HEIGHT}) is invalid until buffers are updated (like calling glClear()). But according to EGL 1.5 spec, section 3.5.6 ("Surface Attributes"): "Querying EGL_WIDTH and EGL_HEIGHT returns respectively the width and height, in pixels, of the surface. For a window or pixmap surface, these values are initially equal to the width and height of the native window or pixmap with respect to which the surface was created" This fixes dEQP-EGL.functional.color_clears.* CTS tests v2: - Do not modify attached_{width,height} (Daniel) - Do not update size on resizing window (Brendan) CC: Daniel Stone <daniel@fooishbar.org> CC: Brendan King <brendan.king@imgtec.com> CC: mesa-stable@lists.freedesktop.org Tested-by: Eric Engestrom <eric@engestrom.ch> Tested-by: Chad Versace <chadversary@chromium.org> Reviewed-by: Chad Versace <chadversary@chromium.org> Reviewed-by: Daniel Stone <daniels@collabora.com> (cherry picked from commit 1fe7cbdf)
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This is more of a hack, since glvnd itself should be providing the file. Until that happens, ensure the libs is correctly set to -lGL CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Adam Jackson <ajax@redhat.com> (cherry picked from commit 315c46cf)
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It's not a thing that can work, nor is a wise idea to attempt. v2: Tweak error message (Dylan) CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Adam Jackson <ajax@redhat.com> (v1) (cherry picked from commit 25a9450a)
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The toggles were broken with the introduction of --enable-mangling. Fixing that up might be possible, but it's not worth the complexity since one can rename the libraries at any point. CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Adam Jackson <ajax@redhat.com> (cherry picked from commit d5ac2364)
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This has been a requirement for ages, yet it seems like we never explicitly errored out during configure. CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Adam Jackson <ajax@redhat.com> (cherry picked from commit a7ea7511)
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Fixes: dEQP-GLES2.shaders.struct.uniform.sampler_array_fragment dEQP-GLES2.shaders.struct.uniform.sampler_array_vertex dEQP-GLES2.shaders.struct.uniform.sampler_nested_fragment dEQP-GLES2.shaders.struct.uniform.sampler_nested_vertex Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 69158c45)
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Fixes texturing from EGL images created from cubemap faces, as in dEQP-EGL.functional.image.create.gles2_cubemap_negative_x_rgba_texture Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 9ab6912a)
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- Aug 08, 2018
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Andres Gomez authored
Signed-off-by: Andres Gomez <agomez@igalia.com>
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- Aug 07, 2018
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With a sufficently recent meson, the following warning is produced: WARNING: Passed invalid keyword argument "extra_args". WARNING: This will become a hard error in the future. It seems that compiler.links(args:) is meant here. Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk> Reviewed-and-Tested-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> (cherry picked from commit a48c0659)
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In commit cf54bd5e, dri_sw_winsys.c began using <sys/shm.h> to support the new functions putImageShm, getImageShm in DRI_SWRastLoader. But Android began supporting System V shared memory only in Oreo. Nougat has no shm headers. Fix the build by ifdef'ing out the shm code on Nougat. Fixes: cf54bd5e "drisw: use shared memory when possible" Reviewed-by: Dave Airlie <airlied@redhat.com> Cc: Marc-André Lureau <marcandre.lureau@gmail.com> (cherry picked from commit aaa41cd2)
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os.path.exists doesn't return True for stale symlinks, but they are in the way later, when a link/file with the same name is to be created. For instance it is conceivable that the pointed to file is replaced by a file with a new name, and then the symlink is dead. To handle this check specifically for all existing symlinks to be removed. (This bugged me for some time with a link libXvMCr600.so always being in the way of installing this file) v2: use only os.lexist and replace all instances of os.exist (Dylan Baker) v3: handle directory check correctly (Eric Engestrom) Fixes: f7f1b30f ("meson: extend install_megadrivers script to handle symmlinking") Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>(v2 minus dir check) Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Signed-off-by: Gert Wollny <gert.wollny@collabora.com> (cherry picked from commit 7a46b2d6)
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This is needed to ensure that we don't get blocked waiting for VPM space with bin/render overlapping. Cc: "18.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 1561e498)
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Fixes bad rendering when forcing 2 spills in glxgears. Cc: "18.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 50a8713d)
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Found when debugging register spilling -- we would try to spill the dest of a STVPMV, inserting spill code after entering the last segment. In fact, we were likely to to choose to do this, given that the STVPMV "dest" temp was never read from, making it cheap to spill. Cc: "18.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit f2c0d310)
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The simulator complained that we had write responses outstanding at shader end. It seems that a TMU read does not guarantee that previous TMU writes by the thread have completed, which surprised me. Cc: "18.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 3f9cb2eb)
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Found while forcing some spilling, which creates a lot of short tmua->thrsw->ldtmu sequences. Cc: "18.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit ccbe33af)
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- Aug 06, 2018
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Up to now we've been lucky that the buffer returned was always exactly at the address we requested. Fixes: 144b40db ("intel: aubinator: drop the 1Tb GTT mapping") Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> (cherry picked from commit 35955afa)
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We already guarded all OP_SULDP against out of bound accesses, but we ended up just reusing whatever value was stored in the dest registers. Fixes CTS test shader_image_load_store.incomplete_textures v2: fix for loads not ending up with predicates (bindless_texture) v3: fix replacing the def Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Karol Herbst <kherbst@redhat.com> (cherry picked from commit c3325097)
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v2: need to do MAX{start+count} instead of MAX{count} added piglit tests v3: use malloc Cc: 18.2 <mesa-stable@lists.freedesktop.org> Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit 0f79b201)
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A problem was reported with arm,arm64 targets build due to missing libLLVM shared library dependency with AOSP; to avoid this issue vulkan.radv is built conditionally only when radeonsi is in BOARD_GPU_DRIVERS Fixes: 0ca153f8 ("android: radv: enable build of vulkan.radv HAL module") Reported-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Cc: "18.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 1c7a2433)
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- Aug 02, 2018
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Andres Gomez authored
Tarball distribution is done through "make distcheck". We include the meson targets also into autotools so they won't fail when building from the tarball. Fixes: 6a60beba ("intel/tools: Add an error state to aub translator") Cc: Jason Ekstrand <jason.ekstrand@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: Dylan Baker <dylan.c.baker@intel.com> Signed-off-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> (cherry picked from commit 2d4d1398)
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