- Feb 07, 2015
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Brian Paul authored
Convert the code to try formats from an array rather than a bunch of if/else cases. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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Brian Paul authored
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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Ben Widawsky authored
Blits to or from a y-tiled surface must always be a multiple of the tile size. From page 16 of the HSW PRM (https://01.org/linuxgraphics/sites/default/files/documentation/intel-gfx-prm-osrc-hsw-memory-views.pdf#16 ) "The pitch of a tiled enclosing region must be an integral number of tile widths" Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
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Ben Widawsky authored
An upcoming patch is going to introduce some code here, and having this code organized as the patch does makes it a bit easier to read later. There should be no functional change here. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
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Park, Jeongmin authored
Since only pp_jimenezmlaa uses depth buffer, we can make it optional. Signed-off-by: Marek Olšák <marek.olsak@amd.com>
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Park, Jeongmin authored
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88962 Signed-off-by: Marek Olšák <marek.olsak@amd.com>
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Ben Widawsky authored
As it turns out, we were over-thinking the cause of the hang on Cherryview. It's simply errata for Cherryview. commit 88fea85f Author: Ben Widawsky <benjamin.widawsky@intel.com> Date: Fri Nov 21 10:47:41 2014 -0800 i965/vec4/gen8: Handle the MUL dest hazard exception This is an explanation to why we never saw the hang on BDW. NOTE: The problem the original patch was trying to fix does still exist. It will have to be fixed at some point. v2: Modify commit message, s/CHV/BDW Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84212 Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Matt Turner <mattst88@gmail.com>
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Emil Velikov authored
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
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Emil Velikov authored
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> (cherry picked from commit 54da987b)
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Emil Velikov authored
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> (cherry picked from commit 62eb27ac)
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- Feb 06, 2015
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Emma Anholt authored
We've probably never seen this ridiculous pattern in the wild, so it didn't matter. Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
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Emma Anholt authored
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
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Emma Anholt authored
I wanted all of these for NIR-to-TGSI. Reviewed-by: Roland Scheidegger <sroland@vmware.com>
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Emma Anholt authored
I wanted to use it for nir-to-tgsi. The equivalent ureg_src_register() is also located here. Reviewed-by: Roland Scheidegger <sroland@vmware.com>
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Marek Olšák authored
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
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Marek Olšák authored
This expects (0,0,0,0), though it can be changed to something else or allow more than one set of values to be considered correct. This is currently the radeonsi behavior. Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
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Marek Olšák authored
v2: allow one of the two values
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Marek Olšák authored
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
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Marek Olšák authored
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
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Marek Olšák authored
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Xavier Bouchoux authored
ADD R6.y.1, R5.w.1, ~1|3f800000 ADD R6.y.2, |R6.y.1|, -0.0001|b8d1b717 was wrongly being converted to ADD R6.y.1, R5.w.1, ~1|3f800000 ADD R6.y.2, R5.w.1, -1.0001|bf800347 because abs() modifier was ignored. Signed-off-by: Xavier Bouchoux <xavierb@gmail.com> Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
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Xavier Bouchoux authored
Since alu does not support abs() modifier on source operands, spill and apply the modifiers to a temp register when needed. Signed-off-by: Xavier Bouchoux <xavierb@gmail.com> Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
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David Heidelberger authored
v2: incorporated changes from Marek Olšák Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: David Heidelberg <david@ixit.cz>
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Iago Toral authored
v2 (Ian Romanick) - Move the check to the lexer before rallocing a copy of the large string. Fixes the following 2 dEQP tests: dEQP-GLES3.functional.shaders.keywords.invalid_identifiers.max_length_vertex dEQP-GLES3.functional.shaders.keywords.invalid_identifiers.max_length_fragment Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
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Kenneth Graunke authored
We were incorrectly attributing VS time to FS8 on Gen8+, which now use fs_visitor for vertex shaders. We don't hit this for geometry shaders yet, but we may as well add support now - the fix is obvious, and we'll just forget later. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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Kenneth Graunke authored
Previously, we special cased FB writes and URB writes in the register allocation code. What we really wanted was to handle any message with EOT set. This saves us from extending the list with new opcodes in the future. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
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Kenneth Graunke authored
This helper function basically just checks inst->eot, but also asserts that only opcodes we expect to terminate threads have EOT set. As far as I'm aware, we've never had such a bug. Removing it means that we don't have to extend the list for new opcodes. Cherryview and Skylake introduce an optimization where sampler messages can have EOT set; scalar GS/HS/DS will likely introduce new opcodes as well. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
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Michel Dänzer authored
The latter currently implies CPU read access, so only PIPE_USAGE_STAGING can be expected to be fast. Mesa demos src/tests/streaming_rect on Kaveri (radeonsi): Unpatched: 42 frames in 1.023 seconds = 41.056 FPS Patched: 615 frames in 1.000 seconds = 615.000 FPS Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88658 Cc: "10.3 10.4" <mesa-stable@lists.freedestkop.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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- Feb 05, 2015
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Tiziano Bacocco authored
Use a dummy vertex buffer object when vs inputs have no corresponding entries in the vertex declaration. This dummy buffer will give to the shader float4(0,0,0,0). This fixes several artifacts on some games. Signed-off-by: Axel Davy <axel.davy@ens.fr> Signed-off-by: Tiziano Bacocco <tizbac2@gmail.com>
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Axel Davy authored
The drm fd wasn't released, causing a crash for wine tests on nouveau, which seems to have a bug when a lot of device descriptors are open. Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com> Signed-off-by: Axel Davy <axel.davy@ens.fr>
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Axel Davy authored
We weren't releasing hal and ref, causing some issues (threads not released, etc) Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com> Signed-off-by: Axel Davy <axel.davy@ens.fr>
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Axel Davy authored
When on a render node the unique ioctl doesn't work. This patch drops the code to detect the device, which relied on an ioctl, and replaces it by the mesa loader function. The mesa loader function is more complete and won't fail for render-nodes. Alternatively we could also have used the pipe cap to determine the vendor and device id from the driver. Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com> Signed-off-by: Axel Davy <axel.davy@ens.fr>
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Axel Davy authored
Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com> Signed-off-by: Axel Davy <axel.davy@ens.fr>
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Axel Davy authored
Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com> Signed-off-by: Axel Davy <axel.davy@ens.fr>
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Axel Davy authored
Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com> Signed-off-by: Axel Davy <axel.davy@ens.fr>
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Axel Davy authored
Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com> Signed-off-by: Axel Davy <axel.davy@ens.fr>
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Tiziano Bacocco authored
Reviewed-by: Axel Davy <axel.davy@ens.fr> Signed-off-by: Tiziano Bacocco <tizbac2@gmail.com>
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Axel Davy authored
Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com> Signed-off-by: Axel Davy <axel.davy@ens.fr>
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Axel Davy authored
Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com> Signed-off-by: Axel Davy <axel.davy@ens.fr>
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Axel Davy authored
Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com> Signed-off-by: Axel Davy <axel.davy@ens.fr>
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