Commit 92b033a8 authored by Tom Stellard's avatar Tom Stellard
Browse files

radeon/llvm: Fix instruction encoding for r600 family GPUs


Tested-by: Michel Dänzer's avatarMichel Dänzer <michel.daenzer@amd.com>

https://bugs.freedesktop.org/show_bug.cgi?id=55217
parent 24a8e0c3
......@@ -218,8 +218,8 @@ void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
//older alu have different encoding for instructions with one or two src
//parameters.
if (STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst &&
MI.getNumOperands() < 4) {
if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
!(MCDesc.TSFlags & R600_InstFlag::OP3)) {
uint64_t ISAOpCode = InstWord01 & (0x3FFULL << 39);
InstWord01 &= ~(0x3FFULL << 39);
InstWord01 |= ISAOpCode << 1;
......
......@@ -21,3 +21,15 @@
// operand.
#define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
namespace R600_InstFlag {
enum TIF {
TRANS_ONLY = (1 << 0),
TEX = (1 << 1),
REDUCTION = (1 << 2),
FC = (1 << 3),
TRIG = (1 << 4),
OP3 = (1 << 5),
VECTOR = (1 << 6)
//FlagOperand bits 7, 8
};
}
......@@ -129,17 +129,4 @@ namespace llvm {
} // End llvm namespace
namespace R600_InstFlag {
enum TIF {
TRANS_ONLY = (1 << 0),
TEX = (1 << 1),
REDUCTION = (1 << 2),
FC = (1 << 3),
TRIG = (1 << 4),
OP3 = (1 << 5),
VECTOR = (1 << 6)
//FlagOperand bits 7, 8
};
}
#endif // R600INSTRINFO_H_
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