drm/i915 feature pull for v6.9: Features and functionality: - Early transport for panel replay and PSR (Jouni) - New ARL PCI IDs (Matt) - DP TPS4 PHY test pattern support (Khaled) Refactoring and cleanups: - Unify and improve VSC SDP for PSR and non-PSR cases (Jouni) - Refactor memory regions and improve debug logging (Ville) - Rework global state serialization (Ville) - Remove unused CDCLK divider fields (Gustavo) - Unify HDCP connector logging format (Jani) - Use display instead of graphics version in display code (Jani) - Move VBT and opregion debugfs next to the implementation (Jani) - Abstract opregion interface, use opaque type (Jani) Fixes: - Fix MTL stolen memory access (Ville) - Fix initial display plane readout for MTL (Ville) - Fix HPD handling during driver init/shutdown (Imre) - Cursor vblank evasion fixes (Ville) - Various VSC SDP fixes (Jouni) - Allow PSR mode changes without full modeset (Jouni) - Fix CDCLK sanitization on module load for Xe2_LPD (Gustavo) - Fix the max DSC bpc supported by the source (Ankit) - Add missing LNL ALPM AUX wake configuration (Jouni) - Cx0 PHY state readout and verify fixes (Mika) - Fix PSR (panel replay) debugfs for MST connectors (Imre) - Fail HDCP repeater authentication if Type1 device not present (Suraj) - Ratelimit debug logging in vm_fault_ttm (Nirmoy) - Use a fake PCH for MTL because south display is not on the PCH (Haridhar) - Disable DSB for Xe driver for now (José) - Fix some LNL display register changes (Lucas) - Fix build on ChromeOS (Paz Zcharya) - Preserve current shared DPLL for fastsets on Type-C ports (Ville) - Fix state checker warnings for MG/TC/TBT PLLs (Ville) - Fix HDCP repeater ctl register value on errors (Jani) - Allow FBC with CCS modifiers on SKL+ (Ville) - Fix HDCP GGTT pinning (Ville) DRM core changes: - Add ratelimited drm dbg print (Nirmoy) - DPCD PSR early transport macro (Jouni) Merges: - Backmerge drm-next to bring Xe driver to drm-intel-next (Jani)