- 07 Jun, 2022 21 commits
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Use ac nir lower pass to generate these lds load/store ops explicitly. Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by:
Qiang Yu <yuq825@gmail.com> Part-of: <mesa/mesa!16418>
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This will be used for radeonsi to map common I/O location to fixed slots agreed by different shader stages. Reviewed-by:
Timur Kristóf <timur.kristof@gmail.com>
Part-of: <mesa/mesa!16418> -
This is from radeonsi. Reviewed-by:
Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: -
Will be used later. Acked-by:
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Reviewed-by:
Timur Kristóf <timur.kristof@gmail.com>
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For radeonsi which pass this value by argument. Reviewed-by:
Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: -
For loading LS-HS vertex stride by shader argument in radeonsi. Reviewed-by:
Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: -
radeonsi will use it. This can be removed again after radeonsi support radv_nir_lower_abi like lower pass. Reviewed-by:
Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: -
All uniform linking is now done via nir based linker not via this code so we drop that from its name. We also drop a bunch of unused parameters. Reviewed-by:
Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!16880>
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As per the comment this was meant to tidy things up after varying linking but varying linking has been moved into a nir based linker so this extra call is no longer needed. This optimisation pass is still called in the regular glsl ir optimisation loop. No shader-db change on Iris (BDW). Reviewed-by:
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Now that we don't need to know if HW binning actually will get used or not, we can just emit the tile loads into the start of the draw CS. Part-of: <mesa/mesa!16826>
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This ends up being needed for moving tile loads into the draw cs. Signed-off-by:
Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <mesa/mesa!16826> -
We have to use a 3D draw to make it possible (so it goes through the binner's visibility calcs), but hopefully the increased overhead for apps with non-skippable rendering balances against skipping in others. The real motivation is to get draw-time state out of tile load setup. Part-of: <mesa/mesa!16826>
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Part-of: <mesa/mesa!16826>
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It means the clear's draw can get skipped when it doesn't intersect with the tile. Part-of: <mesa/mesa!16826>
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Part-of: <mesa/mesa!16826>
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This is just a couple of seconds of runtime. Part-of: <!16826>
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When !fb->binning but fb->binning_possible, we can just set the VSC per-tile visibility reg to all visible in the "whoops, we'd rather not bin but we had to anyway for XFB" case. This gets that EndRenderPass state out of tile_load_cs/store_cs. Part-of: <mesa/mesa!16826>
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This is mostly about helping me understand which choices are constant for the object as opposed to runtime decisions. Part-of: <mesa/mesa!16826>
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Reduce redundant code, make the used SET_VISIBILITY_OVERRIDE value clearer. Part-of: <mesa/mesa!16826>
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They won't get called, so don't bother. Part-of: <mesa/mesa!16826>
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- 06 Jun, 2022 19 commits
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These shaders are near the instruction count limit, and something changed. Part-of: <mesa/mesa!16896>
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One less button to click. Part-of: <mesa/mesa!16896>
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Scenario we want to avoid is double close of DRM fd in iris driver. Signed-off-by:
Nagappa Koppad, Basanagouda <basanagouda.nagappa.koppad@intel.com> Cc: mesa-stable Closes: #6620 Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: 
Kenneth Graunke <kenneth@whitecape.org>
Part-of: <!16886> -
Update the Panfrost driver documentation and the Mesa 22.2 release notes to advertise the new Valhall support. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <!16890> -
Everything required for conformant OpenGL ES 3.1 support on Valhall (v9) is now upstream -- all that's left is to enable implementations! Add the GPU ID for the Mali-G57 implemented in the MediaTek MT8192 system-on-chip. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <mesa/mesa!16890> -
fossil-db (Sienna Cichlid): Totals from 700 (0.43% of 162353) affected shaders: MaxWaves: 18986 -> 18990 (+0.02%) Instrs: 546475 -> 539729 (-1.23%); split: -1.24%, +0.00% CodeSize: 2823716 -> 2808504 (-0.54%); split: -0.55%, +0.01% VGPRs: 25304 -> 25288 (-0.06%) Latency: 2180102 -> 2168187 (-0.55%); split: -0.55%, +0.01% InvThroughput: 466223 -> 457326 (-1.91%) VClause: 6768 -> 6797 (+0.43%); split: -0.01%, +0.44% SClause: 12235 -> 12237 (+0.02%); split: -0.22%, +0.24% Copies: 34498 -> 34479 (-0.06%); split: -0.21%, +0.15% PreVGPRs: 20968 -> 20958 (-0.05%) Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <mesa/mesa!15862> -
Could be enabled/disabled by MESA_HW_ACCEL_SELECT. Reviewed-by:
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There's no way currently in virgl to determine whether it's running above CPU or GPU. This info will be used to disable HW SELECT. Reviewed-by:
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This field can be used to disable some unsupport/unproper hardware acceleration. Reset it when zink is runing on cpu rendering. Reviewed-by:
Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
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Use an internal geometry shader to handle input primitives. Do full accurate culling and clipping in the shader and output hit result and min/max depth to a SSBO for final being written to select buffer. With multiple result slots in SSBO we can left multiple draws on the fly and wait them done when buffer is full or exit GL_SELECT mode. This provides quicker selection response compared to software based solution. Tested on Discovery Studio 2020: some complex model needs 1~2s selection response time originally, now it's almost selected immidiately. Reviewed-by:
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Will be used by geometry shader to store hit result. Reviewed-by:
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Used when in glBegin/End section and HW GL_RENDER mode. Reviewed-by:
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When glthread not enabled, CurrentClientDispatch and CurrentServerDispatch should be same. This does not cause problems before because OutsideBeginEnd and BeginEnd have same BeginEnd entries, so when CurrentServerDispatch==OutsideBeginEnd CurrentClientDispatch==BeginEnd will call into same BeginEnd _mesa_* functions. But we'll add another dispatch table to replace BeginEnd when HW GL_SELECT mode, so this needs to be fixed. Otherwise some function like _mesa_Rectf which always call with CurrentServerDispatch will go into wrong entries. Reviewed-by:
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Used by GL_SELECT mode dispatch table setup. Reviewed-by:
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For constructing dispatch table used in GL_SELECT mode. Every vertex inserted need to also insert a name stack offset attribute. Reviewed-by:
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HW code path will not flush vertex whenever name stack change. It will save the current name stack and write to select buffer only when no space left or exit select mode. This let us submit multi draws from different name stack at once instead of submit draws for a single name stack then wait it finish before submit next one. Reviewed-by:
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No functional change, just pack existing software based implementation into the HardwareAcceleratedSelect switch, will add hardware implementation in next commit. ctx->Select.NameStackDepth is sure to be <=MAX_NAME_STACK_DEPTH, so removed the overflow check in _mesa_LoadName. Reviewed-by:
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