Commit 7c7b2788 authored by Alex Deucher's avatar Alex Deucher

- Add support for Dualhead on M3/M4 (bug 1760)

parent 08a45118
...@@ -19,7 +19,8 @@ full support for 8, 15, 16 and 24 bit pixel depths, hardware ...@@ -19,7 +19,8 @@ full support for 8, 15, 16 and 24 bit pixel depths, hardware
acceleration of drawing primitives, hardware cursor, video modes up to acceleration of drawing primitives, hardware cursor, video modes up to
1800x1440 @ 70Hz, doublescan modes (e.g., 320x200 and 320x240), gamma 1800x1440 @ 70Hz, doublescan modes (e.g., 320x200 and 320x240), gamma
correction at all pixel depths, a fully programming dot clock and robust correction at all pixel depths, a fully programming dot clock and robust
text mode restoration for VT switching. text mode restoration for VT switching. Dualhead is supported on M3/M4
mobile chips.
.SH SUPPORTED HARDWARE .SH SUPPORTED HARDWARE
The The
.B r128 .B r128
...@@ -108,7 +109,11 @@ are used, the system may hang. ...@@ -108,7 +109,11 @@ are used, the system may hang.
Enable or disable use of an OS-specific framebuffer device interface Enable or disable use of an OS-specific framebuffer device interface
(which is not supported on all OSs). See fbdevhw(__drivermansuffix__) (which is not supported on all OSs). See fbdevhw(__drivermansuffix__)
for further information. for further information.
Default: off. Default:
.BI on
for PowerPC,
.BI off
for other architectures.
.TP .TP
.BI "Option \*qDMAForXv\*q \*q" boolean \*q .BI "Option \*qDMAForXv\*q \*q" boolean \*q
Try or don't try to use DMA for Xv image transfers. This will reduce CPU Try or don't try to use DMA for Xv image transfers. This will reduce CPU
...@@ -135,6 +140,12 @@ on PowerPC and ...@@ -135,6 +140,12 @@ on PowerPC and
.B on .B on
on other architectures. on other architectures.
.PP
.B Dualhead Note:
Changing modes on crtc2 in dualhead mode causes problems in
some configurations. The workaround is to switch the mode, change to another
VT, then change back.
.SH "SEE ALSO" .SH "SEE ALSO"
__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) __xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
.SH AUTHORS .SH AUTHORS
......
...@@ -53,6 +53,8 @@ ...@@ -53,6 +53,8 @@
/* Xv support */ /* Xv support */
#include "xf86xv.h" #include "xf86xv.h"
#include "r128_probe.h"
/* DRI support */ /* DRI support */
#ifdef XF86DRI #ifdef XF86DRI
#define _XF86DRI_SERVER_ #define _XF86DRI_SERVER_
...@@ -135,6 +137,13 @@ typedef struct { ...@@ -135,6 +137,13 @@ typedef struct {
/* CRTC2 registers */ /* CRTC2 registers */
CARD32 crtc2_gen_cntl; CARD32 crtc2_gen_cntl;
CARD32 crtc2_h_total_disp;
CARD32 crtc2_h_sync_strt_wid;
CARD32 crtc2_v_total_disp;
CARD32 crtc2_v_sync_strt_wid;
CARD32 crtc2_offset;
CARD32 crtc2_offset_cntl;
CARD32 crtc2_pitch;
/* Flat panel registers */ /* Flat panel registers */
CARD32 fp_crtc_h_total_disp; CARD32 fp_crtc_h_total_disp;
...@@ -160,13 +169,29 @@ typedef struct { ...@@ -160,13 +169,29 @@ typedef struct {
CARD32 ppll_div_3; CARD32 ppll_div_3;
CARD32 htotal_cntl; CARD32 htotal_cntl;
/* Computed values for PLL2 */
CARD32 dot_clock_freq_2;
CARD32 pll_output_freq_2;
int feedback_div_2;
int post_div_2;
/* PLL2 registers */
CARD32 p2pll_ref_div;
CARD32 p2pll_div_0;
CARD32 htotal_cntl2;
/* DDA register */ /* DDA register */
CARD32 dda_config; CARD32 dda_config;
CARD32 dda_on_off; CARD32 dda_on_off;
/* DDA2 register */
CARD32 dda2_config;
CARD32 dda2_on_off;
/* Pallet */ /* Pallet */
Bool palette_valid; Bool palette_valid;
CARD32 palette[256]; CARD32 palette[256];
CARD32 palette2[256];
} R128SaveRec, *R128SavePtr; } R128SaveRec, *R128SavePtr;
typedef struct { typedef struct {
...@@ -186,6 +211,16 @@ typedef struct { ...@@ -186,6 +211,16 @@ typedef struct {
DisplayModePtr mode; DisplayModePtr mode;
} R128FBLayout; } R128FBLayout;
typedef enum
{
MT_NONE,
MT_CRT,
MT_LCD,
MT_DFP,
MT_CTV,
MT_STV
} R128MonitorType;
typedef struct { typedef struct {
EntityInfoPtr pEnt; EntityInfoPtr pEnt;
pciVideoPtr PciInfo; pciVideoPtr PciInfo;
...@@ -403,6 +438,14 @@ typedef struct { ...@@ -403,6 +438,14 @@ typedef struct {
Bool VGAAccess; Bool VGAAccess;
/****** Added for dualhead support *******************/
BOOL HasCRTC2; /* M3/M4 */
BOOL IsSecondary; /* second Screen */
BOOL IsPrimary; /* primary Screen */
BOOL UseCRT; /* force use CRT port as primary */
BOOL SwitchingMode;
R128MonitorType DisplayType; /* Monitor connected on*/
} R128InfoRec, *R128InfoPtr; } R128InfoRec, *R128InfoPtr;
#define R128WaitForFifo(pScrn, entries) \ #define R128WaitForFifo(pScrn, entries) \
...@@ -411,6 +454,7 @@ do { \ ...@@ -411,6 +454,7 @@ do { \
info->fifo_slots -= entries; \ info->fifo_slots -= entries; \
} while (0) } while (0)
extern R128EntPtr R128EntPriv(ScrnInfoPtr pScrn);
extern void R128WaitForFifoFunction(ScrnInfoPtr pScrn, int entries); extern void R128WaitForFifoFunction(ScrnInfoPtr pScrn, int entries);
extern void R128WaitForIdle(ScrnInfoPtr pScrn); extern void R128WaitForIdle(ScrnInfoPtr pScrn);
extern void R128EngineReset(ScrnInfoPtr pScrn); extern void R128EngineReset(ScrnInfoPtr pScrn);
......
...@@ -82,6 +82,7 @@ ...@@ -82,6 +82,7 @@
/* Driver data structures */ /* Driver data structures */
#include "r128.h" #include "r128.h"
#include "r128_reg.h" #include "r128_reg.h"
#include "r128_probe.h"
#ifdef XF86DRI #ifdef XF86DRI
#include "r128_sarea.h" #include "r128_sarea.h"
#define _XF86DRI_SERVER_ #define _XF86DRI_SERVER_
...@@ -117,6 +118,8 @@ static struct { ...@@ -117,6 +118,8 @@ static struct {
{ R128_ROP3_ONE, R128_ROP3_ONE } /* GXset */ { R128_ROP3_ONE, R128_ROP3_ONE } /* GXset */
}; };
extern int gR128EntityIndex;
/* Flush all dirty data in the Pixel Cache to memory. */ /* Flush all dirty data in the Pixel Cache to memory. */
void R128EngineFlush(ScrnInfoPtr pScrn) void R128EngineFlush(ScrnInfoPtr pScrn)
{ {
...@@ -1023,7 +1026,7 @@ void R128EngineInit(ScrnInfoPtr pScrn) ...@@ -1023,7 +1026,7 @@ void R128EngineInit(ScrnInfoPtr pScrn)
R128TRACE(("Pitch for acceleration = %d\n", info->pitch)); R128TRACE(("Pitch for acceleration = %d\n", info->pitch));
R128WaitForFifo(pScrn, 2); R128WaitForFifo(pScrn, 2);
OUTREG(R128_DEFAULT_OFFSET, 0); OUTREG(R128_DEFAULT_OFFSET, pScrn->fbOffset);
OUTREG(R128_DEFAULT_PITCH, info->pitch); OUTREG(R128_DEFAULT_PITCH, info->pitch);
R128WaitForFifo(pScrn, 4); R128WaitForFifo(pScrn, 4);
...@@ -1647,6 +1650,25 @@ void R128CCEReleaseIndirect( ScrnInfoPtr pScrn ) ...@@ -1647,6 +1650,25 @@ void R128CCEReleaseIndirect( ScrnInfoPtr pScrn )
&indirect, sizeof(drmR128Indirect)); &indirect, sizeof(drmR128Indirect));
} }
/* This callback is required for multihead cards using XAA */
static
void R128RestoreCCEAccelState(ScrnInfoPtr pScrn)
{
R128InfoPtr info = R128PTR(pScrn);
/* unsigned char *R128MMIO = info->MMIO; needed for OUTREG below */
/*xf86DrvMsg(pScrn->scrnIndex, X_INFO, "===>RestoreCP\n");*/
R128WaitForFifo(pScrn, 1);
/* is this needed on r128
OUTREG( R128_DEFAULT_OFFSET, info->frontPitchOffset);
*/
R128WaitForIdle(pScrn);
/* FIXME: May need to restore other things,
like BKGD_CLK FG_CLK...*/
}
static void R128CCEAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a) static void R128CCEAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a)
{ {
R128InfoPtr info = R128PTR(pScrn); R128InfoPtr info = R128PTR(pScrn);
...@@ -1707,9 +1729,31 @@ static void R128CCEAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a) ...@@ -1707,9 +1729,31 @@ static void R128CCEAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a)
| HARDWARE_PATTERN_PROGRAMMED_ORIGIN | HARDWARE_PATTERN_PROGRAMMED_ORIGIN
| HARDWARE_PATTERN_SCREEN_ORIGIN | HARDWARE_PATTERN_SCREEN_ORIGIN
| BIT_ORDER_IN_BYTE_LSBFIRST); | BIT_ORDER_IN_BYTE_LSBFIRST);
if(!info->IsSecondary && xf86IsEntityShared(pScrn->entityList[0]))
a->RestoreAccelState = R128RestoreCCEAccelState;
} }
#endif #endif
/* This callback is required for multihead cards using XAA */
static
void R128RestoreAccelState(ScrnInfoPtr pScrn)
{
R128InfoPtr info = R128PTR(pScrn);
unsigned char *R128MMIO = info->MMIO;
R128WaitForFifo(pScrn, 2);
OUTREG(R128_DEFAULT_OFFSET, pScrn->fbOffset);
OUTREG(R128_DEFAULT_PITCH, info->pitch);
/* FIXME: May need to restore other things,
like BKGD_CLK FG_CLK...*/
R128WaitForIdle(pScrn);
}
static void R128MMIOAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a) static void R128MMIOAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a)
{ {
R128InfoPtr info = R128PTR(pScrn); R128InfoPtr info = R128PTR(pScrn);
...@@ -1788,6 +1832,22 @@ static void R128MMIOAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a) ...@@ -1788,6 +1832,22 @@ static void R128MMIOAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a)
| LEFT_EDGE_CLIPPING | LEFT_EDGE_CLIPPING
| LEFT_EDGE_CLIPPING_NEGATIVE_X | LEFT_EDGE_CLIPPING_NEGATIVE_X
| SCANLINE_PAD_DWORD; | SCANLINE_PAD_DWORD;
if(xf86IsEntityShared(pScrn->entityList[0]))
{
DevUnion* pPriv;
R128EntPtr pR128Ent;
pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
gR128EntityIndex);
pR128Ent = pPriv->ptr;
/*if there are more than one devices sharing this entity, we
have to assign this call back, otherwise the XAA will be
disabled */
if(pR128Ent->HasSecondary || pR128Ent->BypassSecondary)
a->RestoreAccelState = R128RestoreAccelState;
}
} }
/* Initialize XAA for supported acceleration and also initialize the /* Initialize XAA for supported acceleration and also initialize the
......
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_cursor.c,v 1.6 2003/02/13 20:28:40 tsi Exp $ */ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_cursor.c,v 1.5tsi Exp $ */
/* /*
* Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
* Precision Insight, Inc., Cedar Park, Texas, and * Precision Insight, Inc., Cedar Park, Texas, and
...@@ -72,8 +72,16 @@ static void R128SetCursorColors(ScrnInfoPtr pScrn, int bg, int fg) ...@@ -72,8 +72,16 @@ static void R128SetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
R128InfoPtr info = R128PTR(pScrn); R128InfoPtr info = R128PTR(pScrn);
unsigned char *R128MMIO = info->MMIO; unsigned char *R128MMIO = info->MMIO;
OUTREG(R128_CUR_CLR0, bg); if(info->IsSecondary)
OUTREG(R128_CUR_CLR1, fg); {
OUTREG(R128_CUR2_CLR0, bg);
OUTREG(R128_CUR2_CLR1, fg);
}
else
{
OUTREG(R128_CUR_CLR0, bg);
OUTREG(R128_CUR_CLR1, fg);
}
} }
/* Set cursor position to (x,y) with offset into cursor bitmap at /* Set cursor position to (x,y) with offset into cursor bitmap at
...@@ -94,11 +102,25 @@ static void R128SetCursorPosition(ScrnInfoPtr pScrn, int x, int y) ...@@ -94,11 +102,25 @@ static void R128SetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
if (xorigin >= cursor->MaxWidth) xorigin = cursor->MaxWidth - 1; if (xorigin >= cursor->MaxWidth) xorigin = cursor->MaxWidth - 1;
if (yorigin >= cursor->MaxHeight) yorigin = cursor->MaxHeight - 1; if (yorigin >= cursor->MaxHeight) yorigin = cursor->MaxHeight - 1;
OUTREG(R128_CUR_HORZ_VERT_OFF, R128_CUR_LOCK | (xorigin << 16) | yorigin); if(!info->IsSecondary)
OUTREG(R128_CUR_HORZ_VERT_POSN, (R128_CUR_LOCK {
OUTREG(R128_CUR_HORZ_VERT_OFF, R128_CUR_LOCK | (xorigin << 16) | yorigin);
OUTREG(R128_CUR_HORZ_VERT_POSN, (R128_CUR_LOCK
| ((xorigin ? 0 : x) << 16) | ((xorigin ? 0 : x) << 16)
| (yorigin ? 0 : y))); | (yorigin ? 0 : y)));
OUTREG(R128_CUR_OFFSET, info->cursor_start + yorigin * 16); OUTREG(R128_CUR_OFFSET, info->cursor_start + yorigin * 16);
}
else
{
OUTREG(R128_CUR2_HORZ_VERT_OFF, (R128_CUR2_LOCK
| (xorigin << 16)
| yorigin));
OUTREG(R128_CUR2_HORZ_VERT_POSN, (R128_CUR2_LOCK
| ((xorigin ? 0 : x) << 16)
| (yorigin ? 0 : y)));
OUTREG(R128_CUR2_OFFSET,
info->cursor_start + pScrn->fbOffset + yorigin * 16);
}
} }
/* Copy cursor image from `image' to video memory. R128SetCursorPosition /* Copy cursor image from `image' to video memory. R128SetCursorPosition
...@@ -112,8 +134,16 @@ static void R128LoadCursorImage(ScrnInfoPtr pScrn, unsigned char *image) ...@@ -112,8 +134,16 @@ static void R128LoadCursorImage(ScrnInfoPtr pScrn, unsigned char *image)
int y; int y;
CARD32 save; CARD32 save;
save = INREG(R128_CRTC_GEN_CNTL); if(!info->IsSecondary)
OUTREG(R128_CRTC_GEN_CNTL, save & (CARD32)~R128_CRTC_CUR_EN); {
save = INREG(R128_CRTC_GEN_CNTL);
OUTREG(R128_CRTC_GEN_CNTL, save & (CARD32)~R128_CRTC_CUR_EN);
}
else
{
save = INREG(R128_CRTC2_GEN_CNTL);
OUTREG(R128_CRTC2_GEN_CNTL, save & (CARD32)~R128_CRTC2_CUR_EN);
}
#if X_BYTE_ORDER == X_BIG_ENDIAN #if X_BYTE_ORDER == X_BIG_ENDIAN
switch(info->CurrentLayout.pixel_bytes) { switch(info->CurrentLayout.pixel_bytes) {
...@@ -169,7 +199,11 @@ static void R128LoadCursorImage(ScrnInfoPtr pScrn, unsigned char *image) ...@@ -169,7 +199,11 @@ static void R128LoadCursorImage(ScrnInfoPtr pScrn, unsigned char *image)
} }
OUTREG(R128_CRTC_GEN_CNTL, save); if(!info->IsSecondary)
OUTREG(R128_CRTC_GEN_CNTL, save);
else
OUTREG(R128_CRTC2_GEN_CNTL, save);
} }
/* Hide hardware cursor. */ /* Hide hardware cursor. */
...@@ -178,7 +212,10 @@ static void R128HideCursor(ScrnInfoPtr pScrn) ...@@ -178,7 +212,10 @@ static void R128HideCursor(ScrnInfoPtr pScrn)
R128InfoPtr info = R128PTR(pScrn); R128InfoPtr info = R128PTR(pScrn);
unsigned char *R128MMIO = info->MMIO; unsigned char *R128MMIO = info->MMIO;
OUTREGP(R128_CRTC_GEN_CNTL, 0, ~R128_CRTC_CUR_EN); if(info->IsSecondary)
OUTREGP(R128_CRTC2_GEN_CNTL, 0, ~R128_CRTC2_CUR_EN);
else
OUTREGP(R128_CRTC_GEN_CNTL, 0, ~R128_CRTC_CUR_EN);
} }
/* Show hardware cursor. */ /* Show hardware cursor. */
...@@ -187,7 +224,15 @@ static void R128ShowCursor(ScrnInfoPtr pScrn) ...@@ -187,7 +224,15 @@ static void R128ShowCursor(ScrnInfoPtr pScrn)
R128InfoPtr info = R128PTR(pScrn); R128InfoPtr info = R128PTR(pScrn);
unsigned char *R128MMIO = info->MMIO; unsigned char *R128MMIO = info->MMIO;
OUTREGP(R128_CRTC_GEN_CNTL, R128_CRTC_CUR_EN, ~R128_CRTC_CUR_EN); if(info->IsSecondary)
{
OUTREGP(R128_CRTC2_GEN_CNTL, R128_CRTC2_CUR_EN,
~R128_CRTC2_CUR_EN);
}
else
{
OUTREGP(R128_CRTC_GEN_CNTL, R128_CRTC_CUR_EN, ~R128_CRTC_CUR_EN);
}
} }
/* Determine if hardware cursor is in use. */ /* Determine if hardware cursor is in use. */
......
This diff is collapsed.
...@@ -101,6 +101,8 @@ PciChipsets R128PciChipsets[] = { ...@@ -101,6 +101,8 @@ PciChipsets R128PciChipsets[] = {
{ -1, -1, RES_UNDEFINED } { -1, -1, RES_UNDEFINED }
}; };
int gR128EntityIndex = -1;
/* Return the options for supported chipset 'n'; NULL otherwise */ /* Return the options for supported chipset 'n'; NULL otherwise */
const OptionInfoRec * const OptionInfoRec *
R128AvailableOptions(int chipid, int busid) R128AvailableOptions(int chipid, int busid)
...@@ -137,7 +139,6 @@ R128Probe(DriverPtr drv, int flags) ...@@ -137,7 +139,6 @@ R128Probe(DriverPtr drv, int flags)
int numDevSections, nATIGDev, nR128GDev; int numDevSections, nATIGDev, nR128GDev;
int *usedChips; int *usedChips;
GDevPtr *devSections, *ATIGDevs, *R128GDevs; GDevPtr *devSections, *ATIGDevs, *R128GDevs;
EntityInfoPtr pEnt;
Bool foundScreen = FALSE; Bool foundScreen = FALSE;
int i; int i;
...@@ -183,10 +184,13 @@ R128Probe(DriverPtr drv, int flags) ...@@ -183,10 +184,13 @@ R128Probe(DriverPtr drv, int flags)
if (flags & PROBE_DETECT) if (flags & PROBE_DETECT)
foundScreen = TRUE; foundScreen = TRUE;
else for (i = 0; i < numUsed; i++) { else for (i = 0; i < numUsed; i++) {
pEnt = xf86GetEntityInfo(usedChips[i]); ScrnInfoPtr pScrn;
EntityInfoPtr pEnt;
if (pEnt->active) {
ScrnInfoPtr pScrn = xf86AllocateScreen(drv, 0); pScrn = NULL;
if((pScrn = xf86ConfigPciEntity(pScrn, 0, usedChips[i],
R128PciChipsets, 0, 0, 0, 0, 0)))
{
#ifdef XFree86LOADER #ifdef XFree86LOADER
...@@ -206,11 +210,43 @@ R128Probe(DriverPtr drv, int flags) ...@@ -206,11 +210,43 @@ R128Probe(DriverPtr drv, int flags)
foundScreen = TRUE; foundScreen = TRUE;
xf86ConfigActivePciEntity(pScrn, usedChips[i], R128PciChipsets, pEnt = xf86GetEntityInfo(usedChips[i]);
0, 0, 0, 0, 0);
/* mobility cards support Dual-Head, mark the entity as sharable*/
if(pEnt->chipset == PCI_CHIP_RAGE128LE ||
pEnt->chipset == PCI_CHIP_RAGE128LF ||
pEnt->chipset == PCI_CHIP_RAGE128MF ||
pEnt->chipset == PCI_CHIP_RAGE128ML)
{
static int instance = 0;
DevUnion* pPriv;
xf86SetEntitySharable(usedChips[i]);
xf86SetEntityInstanceForScreen(pScrn,
pScrn->entityList[0], instance);
if(gR128EntityIndex < 0)
{
gR128EntityIndex = xf86AllocateEntityPrivateIndex();
pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
gR128EntityIndex);
if (!pPriv->ptr)
{
R128EntPtr pR128Ent;
pPriv->ptr = xnfcalloc(sizeof(R128EntRec), 1);
pR128Ent = pPriv->ptr;
pR128Ent->IsDRIEnabled = FALSE;
pR128Ent->BypassSecondary = FALSE;
pR128Ent->HasSecondary = FALSE;
pR128Ent->IsSecondaryRestored = FALSE;
}
}
instance++;
} }
xfree(pEnt); xfree(pEnt);
} }
}
xfree(usedChips); xfree(usedChips);
xfree(devSections); xfree(devSections);
......
...@@ -39,6 +39,21 @@ ...@@ -39,6 +39,21 @@
#include "xf86str.h" #include "xf86str.h"
typedef struct
{
Bool IsDRIEnabled;
Bool HasSecondary;
Bool BypassSecondary;
/*These two registers are used to make sure the CRTC2 is
retored before CRTC_EXT, otherwise it could lead to blank screen.*/
Bool IsSecondaryRestored;
Bool RestorePrimary;
ScrnInfoPtr pSecondaryScrn;
ScrnInfoPtr pPrimaryScrn;
} R128EntRec, *R128EntPtr;
/* r128_probe.c */ /* r128_probe.c */
extern const OptionInfoRec * R128AvailableOptions(int, int); extern const OptionInfoRec * R128AvailableOptions(int, int);
extern void R128Identify(int); extern void R128Identify(int);
......
...@@ -76,7 +76,7 @@ ...@@ -76,7 +76,7 @@
#define OUTPLL(addr, val) \ #define OUTPLL(addr, val) \
do { \ do { \
OUTREG8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); \ OUTREG8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x3f) | R128_PLL_WR_EN); \
OUTREG(R128_CLOCK_CNTL_DATA, val); \ OUTREG(R128_CLOCK_CNTL_DATA, val); \
} while (0) } while (0)
...@@ -189,6 +189,9 @@ ...@@ -189,6 +189,9 @@
# define R128_BIOS_DISPLAY_FP (1 << 0) # define R128_BIOS_DISPLAY_FP (1 << 0)
# define R128_BIOS_DISPLAY_CRT (2 << 0) # define R128_BIOS_DISPLAY_CRT (2 << 0)
# define R128_BIOS_DISPLAY_FP_CRT (3 << 0) # define R128_BIOS_DISPLAY_FP_CRT (3 << 0)
/* R128_DUALHEAD is just a flag for the driver;
it doesn't actually correspond to any bits */
# define R128_DUALHEAD 4
#define R128_BIOS_6_SCRATCH 0x0028 #define R128_BIOS_6_SCRATCH 0x0028
#define R128_BIOS_7_SCRATCH 0x002c #define R128_BIOS_7_SCRATCH 0x002c
#define R128_BIOS_ROM 0x0f30 /* PCI */ #define R128_BIOS_ROM 0x0f30 /* PCI */
...@@ -284,6 +287,7 @@ ...@@ -284,6 +287,7 @@
#define R128_CLOCK_CNTL_INDEX 0x0008 #define R128_CLOCK_CNTL_INDEX 0x0008
# define R128_PLL_WR_EN (1 << 7) # define R128_PLL_WR_EN (1 << 7)
# define R128_PLL_DIV_SEL (3 << 8) # define R128_PLL_DIV_SEL (3 << 8)
# define R128_PLL2_DIV_SEL_MASK ~(3 << 8)
#define R128_CLR_CMP_CLR_3D 0x1a24 #define R128_CLR_CMP_CLR_3D 0x1a24
#define R128_CLR_CMP_CLR_DST 0x15c8 #define R128_CLR_CMP_CLR_DST 0x15c8
#define R128_CLR_CMP_CLR_SRC 0x15c4 #define R128_CLR_CMP_CLR_SRC 0x15c4
...@@ -374,15 +378,41 @@ ...@@ -374,15 +378,41 @@
#define R128_CRTC2_CRNT_FRAME 0x0314 #define R128_CRTC2_CRNT_FRAME 0x0314
#define R128_CRTC2_DEBUG 0x031c #define R128_CRTC2_DEBUG 0x031c
#define R128_CRTC2_GEN_CNTL 0x03f8 #define R128_CRTC2_GEN_CNTL 0x03f8
# define R128_CRTC2_DBL_SCAN_EN (1 << 0)
# define R128_CRTC2_CUR_EN (1 << 16)
# define R128_CRTC2_ICON_EN (1 << 20)
# define R128_CRTC2_DISP_DIS (1 << 23)
# define R128_CRTC2_EN (1 << 25)
# define R128_CRTC2_DISP_REQ_EN_B (1 << 26)
#define R128_CRTC2_GUI_TRIG_VLINE 0x0318 #define R128_CRTC2_GUI_TRIG_VLINE 0x0318
#define R128_CRTC2_H_SYNC_STRT_WID 0x0304 #define R128_CRTC2_H_SYNC_STRT_WID 0x0304
# define R128_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
# define R128_CRTC2_H_SYNC_STRT_CHAR (0x1ff << 3)
# define R128_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
# define R128_CRTC2_H_SYNC_WID (0x3f << 16)
# define R128_CRTC2_H_SYNC_WID_SHIFT 16
# define R128_CRTC2_H_SYNC_POL (1 << 23)
#define R128_CRTC2_H_TOTAL_DISP 0x0300 #define R128_CRTC2_H_TOTAL_DISP 0x0300
# define R128_CRTC2_H_TOTAL (0x01ff << 0)
# define R128_CRTC2_H_TOTAL_SHIFT 0
# define R128_CRTC2_H_DISP (0x00ff << 16)
# define R128_CRTC2_H_DISP_SHIFT 16
#define R128_CRTC2_OFFSET 0x0324 #define R128_CRTC2_OFFSET 0x0324
#define R128_CRTC2_OFFSET_CNTL 0x0328 #define R128_CRTC2_OFFSET_CNTL 0x0328
# define R128_CRTC2_TILE_EN (1 << 15)
#define R128_CRTC2_PITCH 0x032c #define R128_CRTC2_PITCH 0x032c
#define R128_CRTC2_STATUS 0x03fc #define R128_CRTC2_STATUS 0x03fc
#define R128_CRTC2_V_SYNC_STRT_WID 0x030c #define R128_CRTC2_V_SYNC_STRT_WID 0x030c
# define R128_CRTC2_V_SYNC_STRT (0x7ff << 0)
# define R128_CRTC2_V_SYNC_STRT_SHIFT 0
# define R128_CRTC2_V_SYNC_WID (0x1f << 16)
# define R128_CRTC2_V_SYNC_WID_SHIFT 16
# define R128_CRTC2_V_SYNC_POL (1 << 23)
#define R128_CRTC2_V_TOTAL_DISP 0x0308 #define R128_CRTC2_V_TOTAL_DISP 0x0308
# define R128_CRTC2_V_TOTAL (0x07ff << 0)
# define R128_CRTC2_V_TOTAL_SHIFT 0
# define R128_CRTC2_V_DISP (0x07ff << 16)
# define R128_CRTC2_V_DISP_SHIFT 16
#define R128_CRTC2_VLINE_CRNT_VLINE 0x0310 #define R128_CRTC2_VLINE_CRNT_VLINE 0x0310
#define R128_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ #define R128_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
#define R128_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ #define R128_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
...@@ -392,12 +422,19 @@ ...@@ -392,12 +422,19 @@
#define R128_CUR_HORZ_VERT_POSN 0x0264 #define R128_CUR_HORZ_VERT_POSN 0x0264
#define R128_CUR_OFFSET 0x0260 #define R128_CUR_OFFSET 0x0260
# define R128_CUR_LOCK (1 << 31) # define R128_CUR_LOCK (1 << 31)
#define R128_CUR2_CLR0 0x036c
#define R128_CUR2_CLR1 0x0370
#define R128_CUR2_HORZ_VERT_OFF 0x0368
#define R128_CUR2_HORZ_VERT_POSN 0x0364
#define R128_CUR2_OFFSET 0x0360
# define R128_CUR2_LOCK (1 << 31)
#define R128_DAC_CNTL 0x0058 #define R128_DAC_CNTL 0x0058
# define R128_DAC_RANGE_CNTL (3 << 0) # define R128_DAC_RANGE_CNTL (3 << 0)
# define R128_DAC_BLANKING (1 << 2) # define R128_DAC_BLANKING (1 << 2)
# define R128_DAC_CRT_SEL_CRTC2 (1 << 4) # define R128_DAC_CRT_SEL_CRTC2 (1 << 4)
# define R128_DAC_PALETTE_ACC_CTL (1 << 5) # define R128_DAC_PALETTE_ACC_CTL (1 << 5)
# define R128_DAC_PALETTE2_SNOOP_EN (1 << 6)
# define R128_DAC_8BIT_EN (1 << 8) # define R128_DAC_8BIT_EN (1 << 8)
# define R128_DAC_VGA_ADR_EN (1 << 13) # define R128_DAC_VGA_ADR_EN (1 << 13)
# define R128_DAC_MASK_ALL (0xff << 24) # define R128_DAC_MASK_ALL (0xff << 24)
...@@ -408,11 +445,16 @@ ...@@ -408,11 +445,16 @@
#define R128_DAC_W_INDEX 0x03c8 /* VGA */ #define R128_DAC_W_INDEX 0x03c8 /* VGA */
#define R128_DDA_CONFIG 0x02e0 #define R128_DDA_CONFIG 0x02e0
#define R128_DDA_ON_OFF 0x02e4 #define R128_DDA_ON_OFF 0x02e4
#define R128_DDA2_CONFIG 0x03e0
#define R128_DDA2_ON_OFF 0x03e4
#define R128_DEFAULT_OFFSET 0x16e0 #define R128_DEFAULT_OFFSET 0x16e0
#define R128_DEFAULT_PITCH 0x16e4 #define R128_DEFAULT_PITCH 0x16e4
#define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 #define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
# define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) # define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
# define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) # define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
#define R128_DEFAULT2_OFFSET 0x16f8
#define R128_DEFAULT2_PITCH 0x16fc
#define R128_DEFAULT2_SC_BOTTOM_RIGHT 0x16dc
#define R128_DESTINATION_3D_CLR_CMP_VAL 0x1820 #define R128_DESTINATION_3D_CLR_CMP_VAL 0x1820
#define R128_DESTINATION_3D_CLR_CMP_MSK 0x1824 #define R128_DESTINATION_3D_CLR_CMP_MSK 0x1824
#define R128_DEVICE_ID 0x0f02 /* PCI */ #define R128_DEVICE_ID 0x0f02 /* PCI */
...@@ -670,6 +712,7 @@ ...@@ -670,6 +712,7 @@
#define R128_HOST_DATA_LAST 0x17e0 #define R128_HOST_DATA_LAST 0x17e0
#define R128_HOST_PATH_CNTL 0x0130 #define R128_HOST_PATH_CNTL 0x0130
#define R128_HTOTAL_CNTL 0x0009 /* PLL */ #define R128_HTOTAL_CNTL 0x0009 /* PLL */
#define R128_HTOTAL2_CNTL 0x002e /* PLL */
#define R128_HW_DEBUG 0x0128 #define R128_HW_DEBUG 0x0128
#define R128_HW_DEBUG2 0x011c #define R128_HW_DEBUG2 0x011c
...@@ -875,6 +918,19 @@ ...@@ -875,6 +918,19 @@
# define R128_PPLL_REF_DIV_MASK 0x03ff # define R128_PPLL_REF_DIV_MASK 0x03ff
# define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ # define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
# define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ # define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
#define R128_P2PLL_CNTL 0x002a /* P2PLL */
# define R128_P2PLL_RESET (1 << 0)
# define R128_P2PLL_SLEEP (1 << 1)
# define R128_P2PLL_ATOMIC_UPDATE_EN (1 << 16)
# define R128_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
# define R128_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
#define R128_P2PLL_DIV_0 0x002c
# define R128_P2PLL_FB0_DIV_MASK 0x07ff
# define R128_P2PLL_POST0_DIV_MASK 0x00070000