Commit 8ae0e44e authored by Eric Anholt's avatar Eric Anholt

Move to kernel coding style.

We've talked about doing this since the start of the project, putting it off
until "some convenient time".  Just after removing a third of the driver seems
like a convenient time, when backporting's probably not happening much anyway.
parent b9b159c4
......@@ -37,68 +37,71 @@
#include <err.h>
#ifndef DEFFILEMODE
#define DEFFILEMODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) /* 0666*/
#define DEFFILEMODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) /* 0666 */
#endif
static void usage(void)
{
fprintf(stderr, "usage: bios_dumper <filename>\n");
exit(1);
fprintf(stderr, "usage: bios_dumper <filename>\n");
exit(1);
}
int main(int argc, char **argv)
{
struct pci_device *dev;
void *bios;
int err, fd;
struct pci_device *dev;
void *bios;
int err, fd;
if (argc != 2)
usage();
if (argc != 2)
usage();
err = pci_system_init();
if (err != 0) {
fprintf(stderr, "Couldn't initialize PCI system: %s\n", strerror(err));
exit(1);
}
err = pci_system_init();
if (err != 0) {
fprintf(stderr, "Couldn't initialize PCI system: %s\n",
strerror(err));
exit(1);
}
/* Grab the graphics card */
dev = pci_device_find_by_slot(0, 0, 2, 0);
if (dev == NULL)
errx(1, "Couldn't find graphics card");
/* Grab the graphics card */
dev = pci_device_find_by_slot(0, 0, 2, 0);
if (dev == NULL)
errx(1, "Couldn't find graphics card");
err = pci_device_probe(dev);
if (err != 0) {
fprintf(stderr, "Couldn't probe graphics card: %s\n", strerror(err));
exit(1);
}
err = pci_device_probe(dev);
if (err != 0) {
fprintf(stderr, "Couldn't probe graphics card: %s\n",
strerror(err));
exit(1);
}
if (dev->vendor_id != 0x8086)
errx(1, "Graphics card is non-intel");
if (dev->vendor_id != 0x8086)
errx(1, "Graphics card is non-intel");
bios = malloc(dev->rom_size);
if (bios == NULL)
errx(1, "Couldn't allocate memory for BIOS data\n");
bios = malloc(dev->rom_size);
if (bios == NULL)
errx(1, "Couldn't allocate memory for BIOS data\n");
err = pci_device_read_rom(dev, bios);
if (err != 0) {
fprintf(stderr, "Couldn't read graphics card ROM: %s\n",
strerror(err));
exit(1);
}
err = pci_device_read_rom(dev, bios);
if (err != 0) {
fprintf(stderr, "Couldn't read graphics card ROM: %s\n",
strerror(err));
exit(1);
}
fd = open(argv[1], O_RDWR | O_CREAT | O_TRUNC, DEFFILEMODE);
if (fd < 0) {
fprintf(stderr, "Couldn't open output: %s\n", strerror(errno));
exit(1);
}
fd = open(argv[1], O_RDWR | O_CREAT | O_TRUNC, DEFFILEMODE);
if (fd < 0) {
fprintf(stderr, "Couldn't open output: %s\n", strerror(errno));
exit(1);
}
if (write(fd, bios, dev->rom_size) < dev->rom_size) {
fprintf(stderr, "Couldn't write BIOS data: %s\n", strerror(errno));
exit(1);
}
if (write(fd, bios, dev->rom_size) < dev->rom_size) {
fprintf(stderr, "Couldn't write BIOS data: %s\n",
strerror(errno));
exit(1);
}
close(fd);
pci_system_cleanup();
close(fd);
pci_system_cleanup();
return 0;
return 0;
}
This diff is collapsed.
......@@ -41,70 +41,72 @@
#include "../i830_bios.h"
#ifndef DEFFILEMODE
#define DEFFILEMODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) /* 0666*/
#define DEFFILEMODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) /* 0666 */
#endif
static uint32_t read32(void *base, int reg)
{
uint32_t *addr = (uint32_t *)((unsigned char *)(base) + reg);
uint32_t *addr = (uint32_t *) ((unsigned char *)(base) + reg);
return *addr;
return *addr;
}
#if 0
static void write32(void *base, int reg, uint32_t val)
{
uint32_t *addr = (uint32_t *)((unsigned char *)(base) + reg);
*addr = val;
uint32_t *addr = (uint32_t *) ((unsigned char *)(base) + reg);
*addr = val;
}
#endif
static void usage(void)
{
fprintf(stderr, "usage: swf_dumper\n");
exit(1);
fprintf(stderr, "usage: swf_dumper\n");
exit(1);
}
int main(int argc, char **argv)
{
struct pci_device *dev;
int err;
void *addr;
if (argc != 1)
usage();
err = pci_system_init();
if (err != 0) {
fprintf(stderr, "Couldn't initialize PCI system: %s\n", strerror(err));
exit(1);
}
/* Grab the graphics card */
dev = pci_device_find_by_slot(0, 0, 2, 0);
if (dev == NULL)
errx(1, "Couldn't find graphics card");
err = pci_device_probe(dev);
if (err != 0) {
fprintf(stderr, "Couldn't probe graphics card: %s\n", strerror(err));
exit(1);
}
if (dev->vendor_id != 0x8086)
errx(1, "Graphics card is non-intel");
err = pci_device_map_range(dev, dev->regions[0].base_addr,
dev->regions[0].size,
PCI_DEV_MAP_FLAG_WRITABLE, &addr);
if (err) {
fprintf(stderr, "Couldn't map MMIO space: %s\n", strerror(err));
exit(1);
}
printf("SWF14: 0x%08x\n", read32(addr, SWF14));
pci_system_cleanup();
return 0;
struct pci_device *dev;
int err;
void *addr;
if (argc != 1)
usage();
err = pci_system_init();
if (err != 0) {
fprintf(stderr, "Couldn't initialize PCI system: %s\n",
strerror(err));
exit(1);
}
/* Grab the graphics card */
dev = pci_device_find_by_slot(0, 0, 2, 0);
if (dev == NULL)
errx(1, "Couldn't find graphics card");
err = pci_device_probe(dev);
if (err != 0) {
fprintf(stderr, "Couldn't probe graphics card: %s\n",
strerror(err));
exit(1);
}
if (dev->vendor_id != 0x8086)
errx(1, "Graphics card is non-intel");
err = pci_device_map_range(dev, dev->regions[0].base_addr,
dev->regions[0].size,
PCI_DEV_MAP_FLAG_WRITABLE, &addr);
if (err) {
fprintf(stderr, "Couldn't map MMIO space: %s\n", strerror(err));
exit(1);
}
printf("SWF14: 0x%08x\n", read32(addr, SWF14));
pci_system_cleanup();
return 0;
}
This diff is collapsed.
This diff is collapsed.
......@@ -49,54 +49,49 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "i830_ring.h"
#include "i915_drm.h"
unsigned long
intel_get_pixmap_pitch(PixmapPtr pPix)
unsigned long intel_get_pixmap_pitch(PixmapPtr pPix)
{
return (unsigned long)pPix->devKind;
return (unsigned long)pPix->devKind;
}
void
I830Sync(ScrnInfoPtr pScrn)
void I830Sync(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
I830Ptr pI830 = I830PTR(pScrn);
if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC))
ErrorF("I830Sync\n");
if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC))
ErrorF("I830Sync\n");
if (!pScrn->vtSema || !pI830->batch_bo)
return;
if (!pScrn->vtSema || !pI830->batch_bo)
return;
I830EmitFlush(pScrn);
I830EmitFlush(pScrn);
intel_batch_flush(pScrn, TRUE);
intel_batch_wait_last(pScrn);
intel_batch_flush(pScrn, TRUE);
intel_batch_wait_last(pScrn);
}
void
I830EmitFlush(ScrnInfoPtr pScrn)
void I830EmitFlush(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
I830Ptr pI830 = I830PTR(pScrn);
int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
if (IS_I965G(pI830))
flags = 0;
if (IS_I965G(pI830))
flags = 0;
{
BEGIN_BATCH(1);
OUT_BATCH(MI_FLUSH | flags);
ADVANCE_BATCH();
}
{
BEGIN_BATCH(1);
OUT_BATCH(MI_FLUSH | flags);
ADVANCE_BATCH();
}
}
#if (ALWAYS_SYNC || ALWAYS_FLUSH)
void
i830_debug_sync(ScrnInfoPtr scrn)
void i830_debug_sync(ScrnInfoPtr scrn)
{
if (ALWAYS_SYNC)
I830Sync(scrn);
else
intel_batch_flush(scrn, FALSE);
if (ALWAYS_SYNC)
I830Sync(scrn);
else
intel_batch_flush(scrn, FALSE);
}
#endif
......@@ -104,61 +99,60 @@ i830_debug_sync(ScrnInfoPtr scrn)
* from the FbInit() function in the SVGA driver, or before ScreenInit
* in a monolithic server.
*/
Bool
I830AccelInit(ScreenPtr pScreen)
Bool I830AccelInit(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
/* Limits are described in the BLT engine chapter under Graphics Data Size
* Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
* 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.
*
* i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.
*
* i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.
* i965 limits 3D surface to 4kB-aligned offset if tiled.
* i965 limits 3D surfaces to w,h of ?,8192.
* i965 limits 3D surface to pitch of 1B - 128kB.
* i965 limits 3D surface pitch alignment to 1 or 2 times the element size.
* i965 limits 3D surface pitch alignment to 512B if tiled.
* i965 limits 3D destination drawing rect to w,h of 8192,8192.
*
* i915 limits 3D textures to 4B-aligned offset if un-tiled.
* i915 limits 3D textures to ~4kB-aligned offset if tiled.
* i915 limits 3D textures to width,height of 2048,2048.
* i915 limits 3D textures to pitch of 16B - 8kB, in dwords.
* i915 limits 3D destination to ~4kB-aligned offset if tiled.
* i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.
* i915 limits 3D destination to pitch 64B-aligned if used with depth.
* i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.
* i915 limits 3D destination to POT aligned pitch if tiled.
* i915 limits 3D destination drawing rect to w,h of 2048,2048.
*
* i845 limits 3D textures to 4B-aligned offset if un-tiled.
* i845 limits 3D textures to ~4kB-aligned offset if tiled.
* i845 limits 3D textures to width,height of 2048,2048.
* i845 limits 3D textures to pitch of 4B - 8kB, in dwords.
* i845 limits 3D destination to 4B-aligned offset if un-tiled.
* i845 limits 3D destination to ~4kB-aligned offset if tiled.
* i845 limits 3D destination to pitch of 8B - 8kB, in dwords.
* i845 limits 3D destination drawing rect to w,h of 2048,2048.
*
* For the tiled issues, the only tiled buffer we draw to should be
* the front, which will have an appropriate pitch/offset already set up,
* so UXA doesn't need to worry.
*/
if (IS_I965G(pI830)) {
pI830->accel_pixmap_offset_alignment = 4 * 2;
pI830->accel_pixmap_pitch_alignment = 64;
pI830->accel_max_x = 8192;
pI830->accel_max_y = 8192;
} else {
pI830->accel_pixmap_offset_alignment = 4;
pI830->accel_pixmap_pitch_alignment = 64;
pI830->accel_max_x = 2048;
pI830->accel_max_y = 2048;
}
return i830_uxa_init(pScreen);
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
/* Limits are described in the BLT engine chapter under Graphics Data Size
* Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
* 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.
*
* i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.
*
* i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.
* i965 limits 3D surface to 4kB-aligned offset if tiled.
* i965 limits 3D surfaces to w,h of ?,8192.
* i965 limits 3D surface to pitch of 1B - 128kB.
* i965 limits 3D surface pitch alignment to 1 or 2 times the element size.
* i965 limits 3D surface pitch alignment to 512B if tiled.
* i965 limits 3D destination drawing rect to w,h of 8192,8192.
*
* i915 limits 3D textures to 4B-aligned offset if un-tiled.
* i915 limits 3D textures to ~4kB-aligned offset if tiled.
* i915 limits 3D textures to width,height of 2048,2048.
* i915 limits 3D textures to pitch of 16B - 8kB, in dwords.
* i915 limits 3D destination to ~4kB-aligned offset if tiled.
* i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.
* i915 limits 3D destination to pitch 64B-aligned if used with depth.
* i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.
* i915 limits 3D destination to POT aligned pitch if tiled.
* i915 limits 3D destination drawing rect to w,h of 2048,2048.
*
* i845 limits 3D textures to 4B-aligned offset if un-tiled.
* i845 limits 3D textures to ~4kB-aligned offset if tiled.
* i845 limits 3D textures to width,height of 2048,2048.
* i845 limits 3D textures to pitch of 4B - 8kB, in dwords.
* i845 limits 3D destination to 4B-aligned offset if un-tiled.
* i845 limits 3D destination to ~4kB-aligned offset if tiled.
* i845 limits 3D destination to pitch of 8B - 8kB, in dwords.
* i845 limits 3D destination drawing rect to w,h of 2048,2048.
*
* For the tiled issues, the only tiled buffer we draw to should be
* the front, which will have an appropriate pitch/offset already set up,
* so UXA doesn't need to worry.
*/
if (IS_I965G(pI830)) {
pI830->accel_pixmap_offset_alignment = 4 * 2;
pI830->accel_pixmap_pitch_alignment = 64;
pI830->accel_max_x = 8192;
pI830->accel_max_y = 8192;
} else {
pI830->accel_pixmap_offset_alignment = 4;
pI830->accel_pixmap_pitch_alignment = 64;
pI830->accel_max_x = 2048;
pI830->accel_max_y = 2048;
}
return i830_uxa_init(pScreen);
}
......@@ -39,113 +39,113 @@
#include "i830_ring.h"
#include "i915_drm.h"
static void
intel_next_batch(ScrnInfoPtr pScrn)
static void intel_next_batch(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
/* The 865 has issues with larger-than-page-sized batch buffers. */
if (IS_I865G(pI830))
pI830->batch_bo = dri_bo_alloc(pI830->bufmgr, "batch", 4096, 4096);
else
pI830->batch_bo = dri_bo_alloc(pI830->bufmgr, "batch", 4096 * 4, 4096);
if (dri_bo_map(pI830->batch_bo, 1) != 0)
FatalError("Failed to map batchbuffer: %s\n", strerror(errno));
pI830->batch_used = 0;
pI830->batch_ptr = pI830->batch_bo->virtual;
/* If we are using DRI2, we don't know when another client has executed,
* so we have to reinitialize our 3D state per batch.
*/
if (pI830->directRenderingType == DRI_DRI2)
pI830->last_3d = LAST_3D_OTHER;
I830Ptr pI830 = I830PTR(pScrn);
/* The 865 has issues with larger-than-page-sized batch buffers. */
if (IS_I865G(pI830))
pI830->batch_bo =
dri_bo_alloc(pI830->bufmgr, "batch", 4096, 4096);
else
pI830->batch_bo =
dri_bo_alloc(pI830->bufmgr, "batch", 4096 * 4, 4096);
if (dri_bo_map(pI830->batch_bo, 1) != 0)
FatalError("Failed to map batchbuffer: %s\n", strerror(errno));
pI830->batch_used = 0;
pI830->batch_ptr = pI830->batch_bo->virtual;
/* If we are using DRI2, we don't know when another client has executed,
* so we have to reinitialize our 3D state per batch.
*/
if (pI830->directRenderingType == DRI_DRI2)
pI830->last_3d = LAST_3D_OTHER;
}
void
intel_batch_init(ScrnInfoPtr pScrn)
void intel_batch_init(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
I830Ptr pI830 = I830PTR(pScrn);
pI830->batch_emit_start = 0;
pI830->batch_emitting = 0;
pI830->batch_emit_start = 0;
pI830->batch_emitting = 0;
intel_next_batch(pScrn);
intel_next_batch(pScrn);
}
void
intel_batch_teardown(ScrnInfoPtr pScrn)
void intel_batch_teardown(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
I830Ptr pI830 = I830PTR(pScrn);
if (pI830->batch_ptr != NULL) {
dri_bo_unmap(pI830->batch_bo);
pI830->batch_ptr = NULL;
if (pI830->batch_ptr != NULL) {
dri_bo_unmap(pI830->batch_bo);
pI830->batch_ptr = NULL;
dri_bo_unreference(pI830->batch_bo);
pI830->batch_bo = NULL;
dri_bo_unreference(pI830->batch_bo);
pI830->batch_bo = NULL;
dri_bo_unreference(pI830->last_batch_bo);
pI830->last_batch_bo = NULL;
}
dri_bo_unreference(pI830->last_batch_bo);
pI830->last_batch_bo = NULL;
}
}
void
intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed)
void intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed)
{
I830Ptr pI830 = I830PTR(pScrn);
int ret;
I830Ptr pI830 = I830PTR(pScrn);
int ret;
if (pI830->batch_used == 0)
return;
if (pI830->batch_used == 0)
return;
/* Emit a padding dword if we aren't going to be quad-word aligned. */
if ((pI830->batch_used & 4) == 0) {
*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_NOOP;
pI830->batch_used += 4;
}
/* Emit a padding dword if we aren't going to be quad-word aligned. */
if ((pI830->batch_used & 4) == 0) {
*(uint32_t *) (pI830->batch_ptr + pI830->batch_used) = MI_NOOP;
pI830->batch_used += 4;
}
/* Mark the end of the batchbuffer. */
*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_BATCH_BUFFER_END;
pI830->batch_used += 4;
/* Mark the end of the batchbuffer. */
*(uint32_t *) (pI830->batch_ptr + pI830->batch_used) =
MI_BATCH_BUFFER_END;
pI830->batch_used += 4;
dri_bo_unmap(pI830->batch_bo);
pI830->batch_ptr = NULL;
dri_bo_unmap(pI830->batch_bo);
pI830->batch_ptr = NULL;
ret = dri_bo_exec(pI830->batch_bo, pI830->batch_used, NULL, 0, 0xffffffff);
if (ret != 0)
FatalError("Failed to submit batchbuffer: %s\n", strerror(-ret));
ret =
dri_bo_exec(pI830->batch_bo, pI830->batch_used, NULL, 0,
0xffffffff);
if (ret != 0)
FatalError("Failed to submit batchbuffer: %s\n",
strerror(-ret));
/* Save a ref to the last batch emitted, which we use for syncing
* in debug code.
*/
dri_bo_unreference(pI830->last_batch_bo);
pI830->last_batch_bo = pI830->batch_bo;
pI830->batch_bo = NULL;
/* Save a ref to the last batch emitted, which we use for syncing
* in debug code.
*/
dri_bo_unreference(pI830->last_batch_bo);
pI830->last_batch_bo = pI830->batch_bo;
pI830->batch_bo = NULL;
intel_next_batch(pScrn);
intel_next_batch(pScrn);
/* Mark that we need to flush whatever potential rendering we've done in the
* blockhandler. We could set this less often, but it's probably not worth
* the work.
*/
pI830->need_mi_flush = TRUE;
/* Mark that we need to flush whatever potential rendering we've done in the
* blockhandler. We could set this less often, but it's probably not worth
* the work.
*/
pI830->need_mi_flush = TRUE;
if (pI830->batch_flush_notify)
pI830->batch_flush_notify (pScrn);
if (pI830->batch_flush_notify)
pI830->batch_flush_notify(pScrn);
}
/** Waits on the last emitted batchbuffer to be completed. */
void
intel_batch_wait_last(ScrnInfoPtr scrn)
void intel_batch_wait_last(ScrnInfoPtr scrn)
{
I830Ptr pI830 = I830PTR(scrn);
I830Ptr pI830 = I830PTR(scrn);
/* Map it CPU write, which guarantees it's done. This is a completely
* non performance path, so we don't need anything better.
*/
drm_intel_bo_map(pI830->last_batch_bo, TRUE);
drm_intel_bo_unmap(pI830->last_batch_bo);
/* Map it CPU write, which guarantees it's done. This is a completely
* non performance path, so we don't need anything better.
*/
drm_intel_bo_map(pI830->last_batch_bo, TRUE);
drm_intel_bo_unmap(pI830->last_batch_bo);
}
......@@ -37,63 +37,59 @@ void intel_batch_teardown(ScrnInfoPtr pScrn);
void intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed);
void intel_batch_wait_last(ScrnInfoPtr pScrn);
static inline int
intel_batch_space(I830Ptr pI830)
static inline int intel_batch_space(I830Ptr pI830)
{
return (pI830->batch_bo->size - BATCH_RESERVED) - (pI830->batch_used);
return (pI830->batch_bo->size - BATCH_RESERVED) - (pI830->batch_used);
}
static inline void
intel_batch_require_space(ScrnInfoPtr pScrn, I830Ptr pI830, GLuint sz)
{
assert(sz < pI830->batch_bo->size - 8);
if (intel_batch_space(pI830) < sz)
intel_batch_flush(pScrn, FALSE);
assert(sz < pI830->batch_bo->size - 8);
if (intel_batch_space(pI830) < sz)
intel_batch_flush(pScrn, FALSE);
}
static inline void
intel_batch_start_atomic(ScrnInfoPtr pScrn, unsigned int sz)
static inline void intel_batch_start_atomic(ScrnInfoPtr pScrn, unsigned int sz)
{
I830Ptr pI830 = I830PTR(pScrn);
I830Ptr pI830 = I830PTR(pScrn);
assert(!pI830->in_batch_atomic);
intel_batch_require_space(pScrn, pI830, sz * 4);
assert(!pI830->in_batch_atomic);
intel_batch_require_space(pScrn, pI830, sz * 4);
pI830->in_batch_atomic = TRUE;
pI830->batch_atomic_limit = pI830->batch_used + sz * 4;
pI830->in_batch_atomic = TRUE;
pI830->batch_atomic_limit = pI830->batch_used + sz * 4;
}
static inline void
intel_batch_end_atomic(ScrnInfoPtr pScrn)
static inline void intel_batch_end_atomic(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
I830Ptr pI830 = I830PTR(pScrn);
assert(pI830->in_batch_atomic);
assert(pI830->batch_used <= pI830->batch_atomic_limit);
pI830->in_batch_atomic = FALSE;
assert(pI830->in_batch_atomic);
assert(pI830->batch_used <= pI830->batch_atomic_limit);
pI830->in_batch_atomic = FALSE;
}
static inline void
intel_batch_emit_dword(I830Ptr pI830, uint32_t dword)
static inline void intel_batch_emit_dword(I830Ptr pI830, uint32_t dword)
{
assert(pI830->batch_ptr != NULL);
assert(intel_batch_space(pI830) >= 4);
*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = dword;
pI830->batch_used += 4;
assert(pI830->batch_ptr != NULL);
assert(intel_batch_space(pI830) >= 4);
*(uint32_t *) (pI830->batch_ptr + pI830->batch_used) = dword;
pI830->batch_used += 4;
}