Commit 797d173a authored by Chris Wilson's avatar Chris Wilson

i810: Move into a legacy directory.

The driver is still built but is no longer under active development so
move it and supporting files to a new directory.
Signed-off-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
parent cd61531a
......@@ -156,6 +156,9 @@ AC_OUTPUT([
src/xvmc/shader/Makefile
src/xvmc/shader/mc/Makefile
src/xvmc/shader/vld/Makefile
src/legacy/Makefile
src/legacy/i810/Makefile
src/legacy/i810/xvmc/Makefile
man/Makefile
src/render_program/Makefile
])
......@@ -18,7 +18,7 @@
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
SUBDIRS = xvmc render_program
SUBDIRS = xvmc render_program legacy
# this is obnoxious:
# -module lets us name the module exactly how we want
......@@ -32,35 +32,25 @@ AM_CFLAGS = @CWARNFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \
intel_drv_la_LTLIBRARIES = intel_drv.la
intel_drv_la_LDFLAGS = -module -avoid-version
intel_drv_ladir = @moduledir@/drivers
intel_drv_la_LIBADD = -lm @DRM_LIBS@ -ldrm_intel ../uxa/libuxa.la
intel_drv_la_LIBADD = -lm @DRM_LIBS@ -ldrm_intel ../uxa/libuxa.la legacy/liblegacy.la
intel_drv_la_LIBADD += @PCIACCESS_LIBS@
NULL:=#
INTEL_DRI_SRCS = \
i810_dri.c \
i810_dri.h \
i830_dri.c \
i810_hwmc.c
$(NULL)
INTEL_XVMC_SRCS = \
i830_hwmc.h \
i830_hwmc.c
i830_hwmc.c \
$(NULL)
intel_drv_la_SOURCES = \
brw_defines.h \
brw_structs.h \
common.h \
i810_accel.c \
i810_common.h \
i810_cursor.c \
i810_dga.c \
i810_driver.c \
i810.h \
i810_io.c \
i810_memory.c \
i810_reg.h \
i810_ring.h \
i810_video.c \
i810_wmark.c \
intel_module.c \
i830_3d.c \
i830_accel.c \
i830_batchbuffer.c \
......@@ -80,21 +70,26 @@ intel_drv_la_SOURCES = \
i830_render.c \
i915_render.c \
i965_render.c \
drmmode_display.c
drmmode_display.c \
$(NULL)
EXTRA_DIST = \
$(XMODE_SRCS) \
$(INTEL_DRI_SRCS) \
$(INTEL_XVMC_SRCS)
$(INTEL_XVMC_SRCS) \
$(NULL)
if DRI
intel_drv_la_SOURCES += \
$(INTEL_DRI_SRCS)
$(INTEL_DRI_SRCS) \
$(NULL)
intel_drv_la_LIBADD += \
$(DRI_LIBS)
$(DRI_LIBS) \
$(NULL)
endif
if XVMC
intel_drv_la_SOURCES += \
$(INTEL_XVMC_SRCS)
$(INTEL_XVMC_SRCS) \
$(NULL)
endif
......@@ -143,16 +143,6 @@ static inline void memcpy_volatile(volatile void *dst, const void *src,
} \
} while (0)
/* To remove all debugging, make sure I810_DEBUG is defined as a
* preprocessor symbol, and equal to zero.
*/
#if 1
#define I810_DEBUG 0
#endif
#ifndef I810_DEBUG
#warning "Debugging enabled - expect reduced performance"
extern int I810_DEBUG;
#endif
#define DEBUG_VERBOSE_ACCEL 0x1
#define DEBUG_VERBOSE_SYNC 0x2
......@@ -169,229 +159,6 @@ extern int I810_DEBUG;
*/
#define I810_REG_SIZE 0x80000
#ifndef PCI_CHIP_I810
#define PCI_CHIP_I810 0x7121
#define PCI_CHIP_I810_DC100 0x7123
#define PCI_CHIP_I810_E 0x7125
#define PCI_CHIP_I815 0x1132
#define PCI_CHIP_I810_BRIDGE 0x7120
#define PCI_CHIP_I810_DC100_BRIDGE 0x7122
#define PCI_CHIP_I810_E_BRIDGE 0x7124
#define PCI_CHIP_I815_BRIDGE 0x1130
#endif
#ifndef PCI_CHIP_I830_M
#define PCI_CHIP_I830_M 0x3577
#define PCI_CHIP_I830_M_BRIDGE 0x3575
#endif
#ifndef PCI_CHIP_845_G
#define PCI_CHIP_845_G 0x2562
#define PCI_CHIP_845_G_BRIDGE 0x2560
#endif
#ifndef PCI_CHIP_I855_GM
#define PCI_CHIP_I855_GM 0x3582
#define PCI_CHIP_I855_GM_BRIDGE 0x3580
#endif
#ifndef PCI_CHIP_I865_G
#define PCI_CHIP_I865_G 0x2572
#define PCI_CHIP_I865_G_BRIDGE 0x2570
#endif
#ifndef PCI_CHIP_I915_G
#define PCI_CHIP_I915_G 0x2582
#define PCI_CHIP_I915_G_BRIDGE 0x2580
#endif
#ifndef PCI_CHIP_I915_GM
#define PCI_CHIP_I915_GM 0x2592
#define PCI_CHIP_I915_GM_BRIDGE 0x2590
#endif
#ifndef PCI_CHIP_E7221_G
#define PCI_CHIP_E7221_G 0x258A
/* Same as I915_G_BRIDGE */
#define PCI_CHIP_E7221_G_BRIDGE 0x2580
#endif
#ifndef PCI_CHIP_I945_G
#define PCI_CHIP_I945_G 0x2772
#define PCI_CHIP_I945_G_BRIDGE 0x2770
#endif
#ifndef PCI_CHIP_I945_GM
#define PCI_CHIP_I945_GM 0x27A2
#define PCI_CHIP_I945_GM_BRIDGE 0x27A0
#endif
#ifndef PCI_CHIP_I945_GME
#define PCI_CHIP_I945_GME 0x27AE
#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
#endif
#ifndef PCI_CHIP_IGD_GM
#define PCI_CHIP_IGD_GM 0xA011
#define PCI_CHIP_IGD_GM_BRIDGE 0xA010
#define PCI_CHIP_IGD_G 0xA001
#define PCI_CHIP_IGD_G_BRIDGE 0xA000
#endif
#ifndef PCI_CHIP_G35_G
#define PCI_CHIP_G35_G 0x2982
#define PCI_CHIP_G35_G_BRIDGE 0x2980
#endif
#ifndef PCI_CHIP_I965_Q
#define PCI_CHIP_I965_Q 0x2992
#define PCI_CHIP_I965_Q_BRIDGE 0x2990
#endif
#ifndef PCI_CHIP_I965_G
#define PCI_CHIP_I965_G 0x29A2
#define PCI_CHIP_I965_G_BRIDGE 0x29A0
#endif
#ifndef PCI_CHIP_I946_GZ
#define PCI_CHIP_I946_GZ 0x2972
#define PCI_CHIP_I946_GZ_BRIDGE 0x2970
#endif
#ifndef PCI_CHIP_I965_GM
#define PCI_CHIP_I965_GM 0x2A02
#define PCI_CHIP_I965_GM_BRIDGE 0x2A00
#endif
#ifndef PCI_CHIP_I965_GME
#define PCI_CHIP_I965_GME 0x2A12
#define PCI_CHIP_I965_GME_BRIDGE 0x2A10
#endif
#ifndef PCI_CHIP_G33_G
#define PCI_CHIP_G33_G 0x29C2
#define PCI_CHIP_G33_G_BRIDGE 0x29C0
#endif
#ifndef PCI_CHIP_Q35_G
#define PCI_CHIP_Q35_G 0x29B2
#define PCI_CHIP_Q35_G_BRIDGE 0x29B0
#endif
#ifndef PCI_CHIP_Q33_G
#define PCI_CHIP_Q33_G 0x29D2
#define PCI_CHIP_Q33_G_BRIDGE 0x29D0
#endif
#ifndef PCI_CHIP_GM45_GM
#define PCI_CHIP_GM45_GM 0x2A42
#define PCI_CHIP_GM45_BRIDGE 0x2A40
#endif
#ifndef PCI_CHIP_IGD_E_G
#define PCI_CHIP_IGD_E_G 0x2E02
#define PCI_CHIP_IGD_E_G_BRIDGE 0x2E00
#endif
#ifndef PCI_CHIP_G45_G
#define PCI_CHIP_G45_G 0x2E22
#define PCI_CHIP_G45_G_BRIDGE 0x2E20
#endif
#ifndef PCI_CHIP_Q45_G
#define PCI_CHIP_Q45_G 0x2E12
#define PCI_CHIP_Q45_G_BRIDGE 0x2E10
#endif
#ifndef PCI_CHIP_G41_G
#define PCI_CHIP_G41_G 0x2E32
#define PCI_CHIP_G41_G_BRIDGE 0x2E30
#endif
#ifndef PCI_CHIP_B43_G
#define PCI_CHIP_B43_G 0x2E42
#define PCI_CHIP_B43_G_BRIDGE 0x2E40
#endif
#ifndef PCI_CHIP_IGDNG_D_G
#define PCI_CHIP_IGDNG_D_G 0x0042
#define PCI_CHIP_IGDNG_D_G_BRIDGE 0x0040
#endif
#ifndef PCI_CHIP_IGDNG_M_G
#define PCI_CHIP_IGDNG_M_G 0x0046
#define PCI_CHIP_IGDNG_M_G_BRIDGE 0x0044
#endif
#ifndef PCI_CHIP_SANDYBRIDGE
#define PCI_CHIP_SANDYBRIDGE 0x0102
#define PCI_CHIP_SANDYBRIDGE_BRIDGE 0x0100
#define PCI_CHIP_SANDYBRIDGE_M 0x0106
#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M 0x0104
#endif
#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
#define VENDOR_ID(p) (p)->vendor_id
#define DEVICE_ID(p) (p)->device_id
#define SUBVENDOR_ID(p) (p)->subvendor_id
#define SUBSYS_ID(p) (p)->subdevice_id
#define CHIP_REVISION(p) (p)->revision
#define IS_I810(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810 || \
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_DC100 || \
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_E)
#define IS_I815(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I815)
#define IS_I830(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I830_M)
#define IS_845G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_845_G)
#define IS_I85X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM)
#define IS_I852(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I852_GM || pI810->variant == I852_GME))
#define IS_I855(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I855_GM || pI810->variant == I855_GME))
#define IS_I865G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I865_G)
#define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_E7221_G)
#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
#define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
#define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_G)
#define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810))
#define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM)
#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_B43_G || IS_GM45(pI810))
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q)
#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_D_G)
#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_M_G)
#define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810))
#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || \
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || \
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || \
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || \
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || \
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || \
IS_G4X(pI810) || \
IS_IGDNG(pI810) || \
IS_GEN6(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \
IS_IGD(pI810))
#define IS_I9XX(pI810) (IS_I915G(pI810) || \
IS_I915GM(pI810) || \
IS_I945G(pI810) || \
IS_I945GM(pI810) || \
IS_I965G(pI810) || \
IS_G33CLASS(pI810))
#define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810))
#define IS_GEN6(pI810) ((pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE || \
(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M)
#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810))
/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
#define SUPPORTS_YTILING(pI810) (IS_I965G(intel))
#define GTT_PAGE_SIZE KB(4)
#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))
#define ROUND_DOWN_TO(x, y) ((x) / (y) * (y))
......
......@@ -51,7 +51,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "compiler.h"
#include "xf86PciInfo.h"
#include "xf86Pci.h"
#include "i810_reg.h"
#include "xf86Cursor.h"
#include "xf86xv.h"
#include "vgaHW.h"
......@@ -70,6 +69,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "intel_bufmgr.h"
#include "i915_drm.h"
#include "intel_driver.h"
#include "uxa.h"
Bool i830_uxa_init(ScreenPtr pScreen);
void i830_uxa_create_screen_resources(ScreenPtr pScreen);
......@@ -324,7 +325,7 @@ typedef struct intel_screen_private {
unsigned long LinearAddr;
EntityInfoPtr pEnt;
struct pci_device *PciInfo;
uint8_t variant;
struct intel_chipset chipset;
unsigned int BR[20];
......@@ -656,4 +657,6 @@ static inline Bool pixmap_is_scanout(PixmapPtr pixmap)
return pixmap == screen->GetScreenPixmap(screen);
}
const OptionInfoRec *i830_available_options(int chipid, int busid);
#endif /* _I830_H_ */
......@@ -42,7 +42,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "xf86.h"
#include "i830.h"
#include "i810_reg.h"
#include "i915_drm.h"
unsigned long intel_get_pixmap_pitch(PixmapPtr pixmap)
......
......@@ -36,6 +36,7 @@
#include "xf86.h"
#include "i830.h"
#include "i830_reg.h"
#include "i915_drm.h"
#define DUMP_BATCHBUFFERS NULL /* "/tmp/i915-batchbuffers.dump" */
......
......@@ -197,11 +197,6 @@ do { \
__FUNCTION__, \
intel->batch_used - intel->batch_emit_start, \
intel->batch_emitting); \
if ((intel->batch_emitting > 8) && \
(I810_DEBUG & DEBUG_ALWAYS_SYNC)) { \
/* Note: not actually syncing, just flushing each batch. */ \
intel_batch_submit(scrn, FALSE); \
} \
intel->batch_emitting = 0; \
} while (0)
......
......@@ -61,6 +61,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "GL/glxtokens.h"
#include "i830.h"
#include "i830_reg.h"
#include "i915_drm.h"
......
......@@ -77,6 +77,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "i830_hwmc.h"
#endif
#include "legacy/legacy.h"
#include <sys/ioctl.h>
#include "i915_drm.h"
#include <xf86drmMode.h>
......@@ -86,72 +88,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NB_OF(x) (sizeof (x) / sizeof (*x))
/* *INDENT-OFF* */
static SymTabRec I830Chipsets[] = {
{PCI_CHIP_I830_M, "i830"},
{PCI_CHIP_845_G, "845G"},
{PCI_CHIP_I855_GM, "852GM/855GM"},
{PCI_CHIP_I865_G, "865G"},
{PCI_CHIP_I915_G, "915G"},
{PCI_CHIP_E7221_G, "E7221 (i915)"},
{PCI_CHIP_I915_GM, "915GM"},
{PCI_CHIP_I945_G, "945G"},
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I945_GME, "945GME"},
{PCI_CHIP_IGD_GM, "Pineview GM"},
{PCI_CHIP_IGD_G, "Pineview G"},
{PCI_CHIP_I965_G, "965G"},
{PCI_CHIP_G35_G, "G35"},
{PCI_CHIP_I965_Q, "965Q"},
{PCI_CHIP_I946_GZ, "946GZ"},
{PCI_CHIP_I965_GM, "965GM"},
{PCI_CHIP_I965_GME, "965GME/GLE"},
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
{PCI_CHIP_GM45_GM, "GM45"},
{PCI_CHIP_IGD_E_G, "4 Series"},
{PCI_CHIP_G45_G, "G45/G43"},
{PCI_CHIP_Q45_G, "Q45/Q43"},
{PCI_CHIP_G41_G, "G41"},
{PCI_CHIP_B43_G, "B43"},
{PCI_CHIP_IGDNG_D_G, "Clarkdale"},
{PCI_CHIP_IGDNG_M_G, "Arrandale"},
{-1, NULL}
};
static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_I830_M, PCI_CHIP_I830_M, NULL},
{PCI_CHIP_845_G, PCI_CHIP_845_G, NULL},
{PCI_CHIP_I855_GM, PCI_CHIP_I855_GM, NULL},
{PCI_CHIP_I865_G, PCI_CHIP_I865_G, NULL},
{PCI_CHIP_I915_G, PCI_CHIP_I915_G, NULL},
{PCI_CHIP_E7221_G, PCI_CHIP_E7221_G, NULL},
{PCI_CHIP_I915_GM, PCI_CHIP_I915_GM, NULL},
{PCI_CHIP_I945_G, PCI_CHIP_I945_G, NULL},
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, NULL},
{PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, NULL},
{PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, NULL},
{PCI_CHIP_IGD_G, PCI_CHIP_IGD_G, NULL},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, NULL},
{PCI_CHIP_G35_G, PCI_CHIP_G35_G, NULL},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, NULL},
{PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, NULL},
{PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, NULL},
{PCI_CHIP_I965_GME, PCI_CHIP_I965_GME, NULL},
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, NULL},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, NULL},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, NULL},
{PCI_CHIP_GM45_GM, PCI_CHIP_GM45_GM, NULL},
{PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, NULL},
{PCI_CHIP_G45_G, PCI_CHIP_G45_G, NULL},
{PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, NULL},
{PCI_CHIP_G41_G, PCI_CHIP_G41_G, NULL},
{PCI_CHIP_B43_G, PCI_CHIP_B43_G, NULL},
{PCI_CHIP_IGDNG_D_G, PCI_CHIP_IGDNG_D_G, NULL},
{PCI_CHIP_IGDNG_M_G, PCI_CHIP_IGDNG_M_G, NULL},
{-1, -1, NULL}
};
/*
* Note: "ColorKey" is provided for compatibility with the i810 driver.
* However, the correct option name is "VideoKey". "ColorKey" usually
......@@ -159,6 +95,7 @@ static PciChipsets I830PciChipsets[] = {
*/
typedef enum {
OPTION_ACCELMETHOD,
OPTION_DRI,
OPTION_VIDEO_KEY,
OPTION_COLOR_KEY,
......@@ -175,6 +112,7 @@ typedef enum {
} I830Opts;
static OptionInfoRec I830Options[] = {
{OPTION_ACCELMETHOD, "AccelMethod", OPTV_ANYSTR, {0}, FALSE},
{OPTION_DRI, "DRI", OPTV_BOOLEAN, {0}, TRUE},
{OPTION_COLOR_KEY, "ColorKey", OPTV_INTEGER, {0}, FALSE},
{OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE},
......@@ -217,15 +155,9 @@ I830DPRINTF(const char *filename, int line, const char *function,
#endif /* #ifdef I830DEBUG */
/* Export I830 options to i830 driver where necessary */
const OptionInfoRec *I830AvailableOptions(int chipid, int busid)
const OptionInfoRec *i830_available_options(int chipid, int busid)
{
int i;
for (i = 0; I830PciChipsets[i].PCIid > 0; i++) {
if (chipid == I830PciChipsets[i].PCIid)
return I830Options;
}
return NULL;
}
static Bool I830GetRec(ScrnInfoPtr scrn)
......@@ -385,135 +317,18 @@ static void i830_detect_chipset(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
MessageType from = X_PROBED;
const char *chipname;
uint32_t capid;
switch (DEVICE_ID(intel->PciInfo)) {
case PCI_CHIP_I830_M:
chipname = "830M";
break;
case PCI_CHIP_845_G:
chipname = "845G";
break;
case PCI_CHIP_I855_GM:
/* Check capid register to find the chipset variant */
pci_device_cfg_read_u32(intel->PciInfo, &capid, I85X_CAPID);
intel->variant =
(capid >> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK;
switch (intel->variant) {
case I855_GM:
chipname = "855GM";
break;
case I855_GME:
chipname = "855GME";
break;
case I852_GM:
chipname = "852GM";
break;
case I852_GME:
chipname = "852GME";
break;
default:
xf86DrvMsg(scrn->scrnIndex, X_INFO,
"Unknown 852GM/855GM variant: 0x%x)\n",
intel->variant);
chipname = "852GM/855GM (unknown variant)";
break;
}
break;
case PCI_CHIP_I865_G:
chipname = "865G";
break;
case PCI_CHIP_I915_G:
chipname = "915G";
break;
case PCI_CHIP_E7221_G:
chipname = "E7221 (i915)";
break;
case PCI_CHIP_I915_GM:
chipname = "915GM";
break;
case PCI_CHIP_I945_G:
chipname = "945G";
break;
case PCI_CHIP_I945_GM:
chipname = "945GM";
break;
case PCI_CHIP_I945_GME:
chipname = "945GME";
break;
case PCI_CHIP_IGD_GM:
chipname = "Pineview GM";
break;
case PCI_CHIP_IGD_G:
chipname = "Pineview G";
break;
case PCI_CHIP_I965_G:
chipname = "965G";
break;
case PCI_CHIP_G35_G:
chipname = "G35";
break;
case PCI_CHIP_I965_Q:
chipname = "965Q";
break;
case PCI_CHIP_I946_GZ:
chipname = "946GZ";
break;
case PCI_CHIP_I965_GM:
chipname = "965GM";
break;
case PCI_CHIP_I965_GME:
chipname = "965GME/GLE";
break;
case PCI_CHIP_G33_G:
chipname = "G33";
break;
case PCI_CHIP_Q35_G:
chipname = "Q35";
break;
case PCI_CHIP_Q33_G:
chipname = "Q33";
break;
case PCI_CHIP_GM45_GM:
chipname = "GM45";
break;
case PCI_CHIP_IGD_E_G:
chipname = "4 Series";
break;
case PCI_CHIP_G45_G:
chipname = "G45/G43";
break;
case PCI_CHIP_Q45_G:
chipname = "Q45/Q43";
break;
case PCI_CHIP_G41_G:
chipname = "G41";
break;
case PCI_CHIP_B43_G:
chipname = "B43";
break;
case PCI_CHIP_IGDNG_D_G:
chipname = "Clarkdale";
break;
case PCI_CHIP_IGDNG_M_G:
chipname = "Arrandale";
break;
default:
chipname = "unknown chipset";
break;
}
xf86DrvMsg(scrn->scrnIndex, X_INFO,
"Integrated Graphics Chipset: Intel(R) %s\n", chipname);
intel_detect_chipset(scrn,
intel->PciInfo,
&intel->chipset);
/* Set the Chipset and ChipRev, allowing config file entries to override. */
if (intel->pEnt->device->chipset && *intel->pEnt->device->chipset) {
scrn->chipset = intel->pEnt->device->chipset;
from = X_CONFIG;
} else if (intel->pEnt->device->chipID >= 0) {
scrn->chipset = (char *)xf86TokenToString(I830Chipsets,
intel->pEnt->device->
chipID);
scrn->chipset = (char *)xf86TokenToString(intel_chipsets,
intel->pEnt->device->chipID);
from = X_CONFIG;
xf86DrvMsg(scrn->scrnIndex, X_CONFIG,
"ChipID override: 0x%04X\n",
......@@ -521,9 +336,8 @@ static void i830_detect_chipset(ScrnInfoPtr scrn)
DEVICE_ID(intel->PciInfo) = intel->pEnt->device->chipID;
} else {
from = X_PROBED;
scrn->chipset = (char *)xf86TokenToString(I830Chipsets,
DEVICE_ID(intel->
PciInfo));
scrn->chipset = (char *)xf86TokenToString(intel_chipsets,
DEVICE_ID(intel->PciInfo));
}
if (intel->pEnt->device->chipRev >= 0) {
......
......@@ -84,7 +84,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "xf86_OSproc.h"
#include "i830.h"
#include "i810_reg.h"
#include "i915_drm.h"
/**
......
......@@ -30,6 +30,73 @@
#define I830_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value)
/* Flush */
#define MI_FLUSH (0x04<<23)
#define MI_WRITE_DIRTY_STATE (1<<4)
#define MI_END_SCENE (1<<3)
#define MI_GLOBAL_SNAPSHOT_COUNT_RESET (1<<3)
#define MI_INHIBIT_RENDER_CACHE_FLUSH (1<<2)
#define MI_STATE_INSTRUCTION_CACHE_FLUSH (1<<1)
#define MI_INVALIDATE_MAP_CACHE (1<<0)
/* broadwater flush bits */
#define BRW_MI_GLOBAL_SNAPSHOT_RESET (1 << 3)
#define MI_BATCH_BUFFER_END (0xA << 23)
/* Noop */
#define MI_NOOP 0x00
#define MI_NOOP_WRITE_ID (1<<22)
#define MI_NOOP_ID_MASK (1<<22 - 1)
/* Wait for Events */
#define MI_WAIT_FOR_EVENT (0x03<<23)
#define MI_WAIT_FOR_PIPEB_SVBLANK (1<<18)
#define MI_WAIT_FOR_PIPEA_SVBLANK (1<<17)
#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
#define MI_WAIT_FOR_PIPEB_VBLANK (1<<7)
#define MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW (1<<5)
#define MI_WAIT_FOR_PIPEA_VBLANK (1<<3)
#define MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW (1<<1)
/* Set the scan line for MI_WAIT_FOR_PIPE?_SCAN_LINE_WINDOW */
#define MI_LOAD_SCAN_LINES_INCL (0x12<<23)
#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEA (0)
#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEB (0x1<<20)
/* BLT commands */
#define COLOR_BLT_CMD ((2<<29)|(0x40<<22)|(0x3))
#define COLOR_BLT_WRITE_ALPHA (1<<21)
#define COLOR_BLT_WRITE_RGB (1<<20)
#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|(0x4))
#define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
#define XY_COLOR_BLT_WRITE_RGB (1<<20)
#define XY_COLOR_BLT_TILED (1<<11)
#define XY_SETUP_CLIP_BLT_CMD ((2<<29)|(3<<22)|1)
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
#define XY_SRC_COPY_BLT_SRC_TILED (1<<15)
#define XY_SRC_COPY_BLT_DST_TILED (1<<11)
#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|0x4)
#define SRC_COPY_BLT_WRITE_ALPHA (1<<21)
#define SRC_COPY_BLT_WRITE_RGB (1<<20)
#define XY_PAT_BLT_IMMEDIATE ((2<<29)|(0x72<<22))
#define XY_MONO_PAT_BLT_CMD ((0x2<<29)|(0x52<<22)|0x7)
#define XY_MONO_PAT_VERT_SEED ((1<<10)|(1<<9)|(1<<8))
#define XY_MONO_PAT_HORT_SEED ((1<<14)|(1<<13)|(1<<12))
#define XY_MONO_PAT_BLT_WRITE_ALPHA (1<<21)
#define XY_MONO_PAT_BLT_WRITE_RGB (1<<20)
#define XY_MONO_SRC_BLT_CMD ((0x2<<29)|(0x54<<22)|(0x6))
#define XY_MONO_SRC_BLT_WRITE_ALPHA (1<<21)
#define XY_MONO_SRC_BLT_WRITE_RGB (1<<20)
#define CMD_3D (0x3<<29)