Commit 5c663ce8 authored by Chris Wilson's avatar Chris Wilson

Rename common infrastructure to the intel namespace.

After splitting out the i810 driver into its own legacy directory, we
can identify the common routines not as i830 but as intel. This
clarifies the code which *is* i830 specific.
Signed-off-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
parent 797d173a
......@@ -37,51 +37,36 @@ intel_drv_la_LIBADD += @PCIACCESS_LIBS@
NULL:=#
INTEL_DRI_SRCS = \
i830_dri.c \
$(NULL)
INTEL_XVMC_SRCS = \
i830_hwmc.h \
i830_hwmc.c \
$(NULL)
intel_drv_la_SOURCES = \
brw_defines.h \
brw_structs.h \
common.h \
intel.h \
intel_module.c \
intel_driver.c \
intel_batchbuffer.c \
intel_batchbuffer.h \
intel_memory.c \
intel_uxa.c \
intel_video.c \
intel_video.h \
i830_3d.c \
i830_accel.c \
i830_batchbuffer.c \
i830_batchbuffer.h \
i830_driver.c \
i830.h \
i830_memory.c \
i830_video.c \
i830_video.h \
i830_render.c \
i830_reg.h \
i915_3d.c \
i915_3d.h \
i915_reg.h \
i915_3d.c \
i915_render.c \
i915_video.c \
i965_reg.h \
i965_video.c \
i830_uxa.c \
i830_render.c \
i915_render.c \
i965_render.c \
drmmode_display.c \
$(NULL)
EXTRA_DIST = \
$(XMODE_SRCS) \
$(INTEL_DRI_SRCS) \
$(INTEL_XVMC_SRCS) \
$(NULL)
if DRI
intel_drv_la_SOURCES += \
$(INTEL_DRI_SRCS) \
intel_dri.c \
$(NULL)
intel_drv_la_LIBADD += \
$(DRI_LIBS) \
......@@ -90,6 +75,7 @@ endif
if XVMC
intel_drv_la_SOURCES += \
$(INTEL_XVMC_SRCS) \
intel_hwmc.h \
intel_hwmc.c \
$(NULL)
endif
......@@ -38,7 +38,7 @@
#include "xorgVersion.h"
#include "i830.h"
#include "intel.h"
#include "intel_bufmgr.h"
#include "xf86drmMode.h"
#include "X11/Xatom.h"
......@@ -402,7 +402,7 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
drmmode_output_dpms(output, DPMSModeOn);
}
i830_set_gem_max_sizes(scrn);
intel_set_gem_max_sizes(scrn);
if (scrn->pScreen)
xf86_reload_cursors(scrn->pScreen);
......@@ -476,7 +476,7 @@ drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width, int height)
unsigned long rotate_pitch;
int ret;
drmmode_crtc->rotate_bo = i830_allocate_framebuffer(scrn,
drmmode_crtc->rotate_bo = intel_allocate_framebuffer(scrn,
width, height,
drmmode->cpp,
&rotate_pitch);
......@@ -536,7 +536,7 @@ drmmode_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
return NULL;
}
i830_set_pixmap_bo(rotate_pixmap, drmmode_crtc->rotate_bo);
intel_set_pixmap_bo(rotate_pixmap, drmmode_crtc->rotate_bo);
intel->shadow_present = TRUE;
......@@ -552,7 +552,7 @@ drmmode_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *dat
drmmode_ptr drmmode = drmmode_crtc->drmmode;
if (rotate_pixmap) {
i830_set_pixmap_bo(rotate_pixmap, NULL);
intel_set_pixmap_bo(rotate_pixmap, NULL);
FreeScratchPixmapHeader(rotate_pixmap);
}
......@@ -1267,7 +1267,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
old_fb_id = drmmode->fb_id;
old_front = intel->front_buffer;
intel->front_buffer = i830_allocate_framebuffer(scrn,
intel->front_buffer = intel_allocate_framebuffer(scrn,
width, height,
intel->cpp,
&pitch);
......@@ -1287,7 +1287,8 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
pixmap = screen->GetScreenPixmap(screen);
screen->ModifyPixmapHeader(pixmap, width, height, -1, -1, pitch, NULL);
i830_set_pixmap_bo(pixmap, intel->front_buffer);
intel_set_pixmap_bo(pixmap, intel->front_buffer);
intel_get_pixmap_private(pixmap)->busy = 1;
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
......
......@@ -30,7 +30,7 @@
#endif
#include "xf86.h"
#include "i830.h"
#include "intel.h"
#include "i830_reg.h"
......
/**************************************************************************
Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sub license, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial portions
of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
*
*/
/*
* XXX So far, for GXxor this is about 40% of the speed of SW, but CPU
* utilisation falls from 95% to < 5%.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "i830.h"
#include "i915_drm.h"
unsigned long intel_get_pixmap_pitch(PixmapPtr pixmap)
{
return (unsigned long)pixmap->devKind;
}
void i830_debug_flush(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
if (intel->debug_flush & DEBUG_FLUSH_CACHES)
intel_batch_emit_flush(scrn);
if (intel->debug_flush & DEBUG_FLUSH_BATCHES)
intel_batch_submit(scrn, FALSE);
}
/* The following function sets up the supported acceleration. Call it
* from the FbInit() function in the SVGA driver, or before ScreenInit
* in a monolithic server.
*/
Bool I830AccelInit(ScreenPtr screen)
{
ScrnInfoPtr scrn = xf86Screens[screen->myNum];
intel_screen_private *intel = intel_get_screen_private(scrn);
/* Limits are described in the BLT engine chapter under Graphics Data Size
* Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
* 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.
*
* i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.
*
* i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.
* i965 limits 3D surface to 4kB-aligned offset if tiled.
* i965 limits 3D surfaces to w,h of ?,8192.
* i965 limits 3D surface to pitch of 1B - 128kB.
* i965 limits 3D surface pitch alignment to 1 or 2 times the element size.
* i965 limits 3D surface pitch alignment to 512B if tiled.
* i965 limits 3D destination drawing rect to w,h of 8192,8192.
*
* i915 limits 3D textures to 4B-aligned offset if un-tiled.
* i915 limits 3D textures to ~4kB-aligned offset if tiled.
* i915 limits 3D textures to width,height of 2048,2048.
* i915 limits 3D textures to pitch of 16B - 8kB, in dwords.
* i915 limits 3D destination to ~4kB-aligned offset if tiled.
* i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.
* i915 limits 3D destination to pitch 64B-aligned if used with depth.
* i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.
* i915 limits 3D destination to POT aligned pitch if tiled.
* i915 limits 3D destination drawing rect to w,h of 2048,2048.
*
* i845 limits 3D textures to 4B-aligned offset if un-tiled.
* i845 limits 3D textures to ~4kB-aligned offset if tiled.
* i845 limits 3D textures to width,height of 2048,2048.
* i845 limits 3D textures to pitch of 4B - 8kB, in dwords.
* i845 limits 3D destination to 4B-aligned offset if un-tiled.
* i845 limits 3D destination to ~4kB-aligned offset if tiled.
* i845 limits 3D destination to pitch of 8B - 8kB, in dwords.
* i845 limits 3D destination drawing rect to w,h of 2048,2048.
*
* For the tiled issues, the only tiled buffer we draw to should be
* the front, which will have an appropriate pitch/offset already set up,
* so UXA doesn't need to worry.
*/
if (IS_I965G(intel)) {
intel->accel_pixmap_offset_alignment = 4 * 2;
intel->accel_pixmap_pitch_alignment = 64;
intel->accel_max_x = 8192;
intel->accel_max_y = 8192;
} else {
intel->accel_pixmap_offset_alignment = 4;
intel->accel_pixmap_pitch_alignment = 64;
intel->accel_max_x = 2048;
intel->accel_max_y = 2048;
}
return i830_uxa_init(screen);
}
......@@ -31,7 +31,7 @@
#endif
#include "xf86.h"
#include "i830.h"
#include "intel.h"
#include "i830_reg.h"
struct blendinfo {
......@@ -251,12 +251,12 @@ static void i830_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit)
uint32_t wrap_mode;
uint32_t texcoordtype;
pitch = intel_get_pixmap_pitch(pixmap);
pitch = intel_pixmap_pitch(pixmap);
intel->scale_units[unit][0] = pixmap->drawable.width;
intel->scale_units[unit][1] = pixmap->drawable.height;
intel->transform[unit] = picture->transform;
if (i830_transform_is_affine(intel->transform[unit]))
if (intel_transform_is_affine(intel->transform[unit]))
texcoordtype = TEXCOORDTYPE_CARTESIAN;
else
texcoordtype = TEXCOORDTYPE_HOMOGENEOUS;
......@@ -292,9 +292,9 @@ static void i830_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit)
}
filter |= (MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT);
if (i830_pixmap_tiled(pixmap)) {
if (intel_pixmap_tiled(pixmap)) {
tiling_bits = TM0S1_TILED_SURFACE;
if (i830_get_pixmap_intel(pixmap)->tiling
if (intel_get_pixmap_private(pixmap)->tiling
== I915_TILING_Y)
tiling_bits |= TM0S1_TILE_WALK;
} else
......@@ -450,9 +450,9 @@ i830_prepare_composite(int op, PicturePtr source_picture,
intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *bo_table[] = {
NULL, /* batch_bo */
i830_get_pixmap_bo(source),
mask ? i830_get_pixmap_bo(mask) : NULL,
i830_get_pixmap_bo(dest),
intel_get_pixmap_bo(source),
mask ? intel_get_pixmap_bo(mask) : NULL,
intel_get_pixmap_bo(dest),
};
intel->render_source_picture = source_picture;
......@@ -488,7 +488,7 @@ i830_prepare_composite(int op, PicturePtr source_picture,
if (!i830_get_dest_format(dest_picture, &intel->render_dest_format))
return FALSE;
if (!i830_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table)))
if (!intel_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table)))
return FALSE;
if (mask) {
......@@ -563,8 +563,8 @@ i830_prepare_composite(int op, PicturePtr source_picture,
intel->s8_blendctl = blendctl;
}
if(i830_uxa_pixmap_is_dirty(source) ||
(mask && i830_uxa_pixmap_is_dirty(mask)))
if(intel_pixmap_is_dirty(source) ||
(mask && intel_pixmap_is_dirty(mask)))
intel_batch_emit_flush(scrn);
intel->needs_render_state_emit = TRUE;
......@@ -585,9 +585,9 @@ static void i830_emit_composite_state(ScrnInfoPtr scrn)
assert(intel->in_batch_atomic);
if (i830_pixmap_tiled(intel->render_dest)) {
if (intel_pixmap_tiled(intel->render_dest)) {
tiling_bits = BUF_3D_TILED_SURFACE;
if (i830_get_pixmap_intel(intel->render_dest)->tiling
if (intel_get_pixmap_private(intel->render_dest)->tiling
== I915_TILING_Y)
tiling_bits |= BUF_3D_TILE_WALK_Y;
} else
......@@ -595,7 +595,7 @@ static void i830_emit_composite_state(ScrnInfoPtr scrn)
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits |
BUF_3D_PITCH(intel_get_pixmap_pitch(intel->render_dest)));
BUF_3D_PITCH(intel_pixmap_pitch(intel->render_dest)));
OUT_RELOC_PIXMAP(intel->render_dest,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
......@@ -636,12 +636,12 @@ static void i830_emit_composite_state(ScrnInfoPtr scrn)
DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
DISABLE_DITHER | ENABLE_COLOR_WRITE | DISABLE_DEPTH_WRITE);
if (i830_transform_is_affine(intel->render_source_picture->transform))
if (intel_transform_is_affine(intel->render_source_picture->transform))
texcoordfmt |= (TEXCOORDFMT_2D << 0);
else
texcoordfmt |= (TEXCOORDFMT_3D << 0);
if (intel->render_mask) {
if (i830_transform_is_affine
if (intel_transform_is_affine
(intel->render_mask_picture->transform))
texcoordfmt |= (TEXCOORDFMT_2D << 2);
else
......@@ -677,23 +677,23 @@ i830_emit_composite_primitive(PixmapPtr dest,
{
float x = srcX, y = srcY;
is_affine_src = i830_transform_is_affine(intel->transform[0]);
is_affine_src = intel_transform_is_affine(intel->transform[0]);
if (is_affine_src) {
if (!i830_get_transformed_coordinates(x, y,
if (!intel_get_transformed_coordinates(x, y,
intel->
transform[0],
&src_x[0],
&src_y[0]))
return;
if (!i830_get_transformed_coordinates(x, y + h,
if (!intel_get_transformed_coordinates(x, y + h,
intel->
transform[0],
&src_x[1],
&src_y[1]))
return;
if (!i830_get_transformed_coordinates(x + w, y + h,
if (!intel_get_transformed_coordinates(x + w, y + h,
intel->
transform[0],
&src_x[2],
......@@ -702,7 +702,7 @@ i830_emit_composite_primitive(PixmapPtr dest,
per_vertex += 2; /* src x/y */
} else {
if (!i830_get_transformed_coordinates_3d(x, y,
if (!intel_get_transformed_coordinates_3d(x, y,
intel->
transform[0],
&src_x[0],
......@@ -710,7 +710,7 @@ i830_emit_composite_primitive(PixmapPtr dest,
&src_w[0]))
return;
if (!i830_get_transformed_coordinates_3d(x, y + h,
if (!intel_get_transformed_coordinates_3d(x, y + h,
intel->
transform[0],
&src_x[1],
......@@ -718,7 +718,7 @@ i830_emit_composite_primitive(PixmapPtr dest,
&src_w[1]))
return;
if (!i830_get_transformed_coordinates_3d(x + w, y + h,
if (!intel_get_transformed_coordinates_3d(x + w, y + h,
intel->
transform[0],
&src_x[2],
......@@ -733,23 +733,23 @@ i830_emit_composite_primitive(PixmapPtr dest,
if (intel->render_mask) {
float x = maskX, y = maskY;
is_affine_mask = i830_transform_is_affine(intel->transform[1]);
is_affine_mask = intel_transform_is_affine(intel->transform[1]);
if (is_affine_mask) {
if (!i830_get_transformed_coordinates(x, y,
if (!intel_get_transformed_coordinates(x, y,
intel->
transform[1],
&mask_x[0],
&mask_y[0]))
return;
if (!i830_get_transformed_coordinates(x, y + h,
if (!intel_get_transformed_coordinates(x, y + h,
intel->
transform[1],
&mask_x[1],
&mask_y[1]))
return;
if (!i830_get_transformed_coordinates(x + w, y + h,
if (!intel_get_transformed_coordinates(x + w, y + h,
intel->
transform[1],
&mask_x[2],
......@@ -758,7 +758,7 @@ i830_emit_composite_primitive(PixmapPtr dest,
per_vertex += 2; /* mask x/y */
} else {
if (!i830_get_transformed_coordinates_3d(x, y,
if (!intel_get_transformed_coordinates_3d(x, y,
intel->
transform[1],
&mask_x[0],
......@@ -766,7 +766,7 @@ i830_emit_composite_primitive(PixmapPtr dest,
&mask_w[0]))
return;
if (!i830_get_transformed_coordinates_3d(x, y + h,
if (!intel_get_transformed_coordinates_3d(x, y + h,
intel->
transform[1],
&mask_x[1],
......@@ -774,7 +774,7 @@ i830_emit_composite_primitive(PixmapPtr dest,
&mask_w[1]))
return;
if (!i830_get_transformed_coordinates_3d(x + w, y + h,
if (!intel_get_transformed_coordinates_3d(x + w, y + h,
intel->
transform[1],
&mask_x[2],
......
......@@ -30,7 +30,7 @@
#endif
#include "xf86.h"
#include "i830.h"
#include "intel.h"
#include "i915_reg.h"
......
This diff is collapsed.
......@@ -34,8 +34,8 @@
#include "xf86xv.h"
#include "fourcc.h"
#include "i830.h"
#include "i830_video.h"
#include "intel.h"
#include "intel_video.h"
#include "i915_reg.h"
#include "i915_3d.h"
......@@ -149,15 +149,15 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn,
DSTORG_VERT_BIAS(0x8) | format);
/* front buffer, pitch, offset */
if (i830_pixmap_tiled(target)) {
if (intel_pixmap_tiled(target)) {
tiling = BUF_3D_TILED_SURFACE;
if (i830_get_pixmap_intel(target)->tiling == I915_TILING_Y)
if (intel_get_pixmap_private(target)->tiling == I915_TILING_Y)
tiling |= BUF_3D_TILE_WALK_Y;
} else
tiling = 0;
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling |
BUF_3D_PITCH(intel_get_pixmap_pitch(target)));
BUF_3D_PITCH(intel_pixmap_pitch(target)));
OUT_RELOC_PIXMAP(target, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
......@@ -477,5 +477,5 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn,
target->drawable.pScreen->DestroyPixmap(target);
}
i830_debug_flush(scrn);
intel_debug_flush(scrn);
}
......@@ -35,7 +35,7 @@
#include <assert.h>
#include "xf86.h"
#include "i830.h"
#include "intel.h"
#include "i830_reg.h"
#include "i965_reg.h"
......@@ -1071,7 +1071,7 @@ i965_set_picture_surface_state(intel_screen_private *intel,
{
struct brw_surface_state_padded *ss;
struct brw_surface_state local_ss;
struct intel_pixmap *priv = i830_get_pixmap_intel(pixmap);
struct intel_pixmap *priv = intel_get_pixmap_private(pixmap);
ss = (struct brw_surface_state_padded *)ss_bo->virtual + ss_index;
......@@ -1107,9 +1107,9 @@ i965_set_picture_surface_state(intel_screen_private *intel,
local_ss.ss2.render_target_rotation = 0;
local_ss.ss2.height = pixmap->drawable.height - 1;
local_ss.ss2.width = pixmap->drawable.width - 1;
local_ss.ss3.pitch = intel_get_pixmap_pitch(pixmap) - 1;
local_ss.ss3.pitch = intel_pixmap_pitch(pixmap) - 1;
local_ss.ss3.tile_walk = 0; /* Tiled X */
local_ss.ss3.tiled_surface = i830_pixmap_tiled(pixmap) ? 1 : 0;
local_ss.ss3.tiled_surface = intel_pixmap_tiled(pixmap) ? 1 : 0;
memcpy(ss, &local_ss, sizeof(local_ss));
......@@ -1163,7 +1163,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
/* Mark the destination dirty within this batch */
intel_batch_mark_pixmap_domains(intel,
i830_get_pixmap_intel(dest),
intel_get_pixmap_private(dest),
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
......@@ -1552,8 +1552,8 @@ i965_prepare_composite(int op, PicturePtr source_picture,
}
/* Flush any pending writes prior to relocating the textures. */
if(i830_uxa_pixmap_is_dirty(source) ||
(mask && i830_uxa_pixmap_is_dirty(mask)))
if (intel_pixmap_is_dirty(source) ||
(mask && intel_pixmap_is_dirty(mask)))
intel_batch_emit_flush(scrn);
......@@ -1632,7 +1632,7 @@ i965_prepare_composite(int op, PicturePtr source_picture,
intel->scale_units[0][1] = source->drawable.height;
intel->transform[0] = source_picture->transform;
composite_op->is_affine = i830_transform_is_affine(intel->transform[0]);
composite_op->is_affine = intel_transform_is_affine(intel->transform[0]);
if (!mask) {
intel->transform[1] = NULL;
......@@ -1643,7 +1643,7 @@ i965_prepare_composite(int op, PicturePtr source_picture,
intel->scale_units[1][0] = mask->drawable.width;
intel->scale_units[1][1] = mask->drawable.height;
composite_op->is_affine &=
i830_transform_is_affine(intel->transform[1]);
intel_transform_is_affine(intel->transform[1]);
}
if (mask) {
......@@ -1735,30 +1735,30 @@ i965_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY,
Bool is_affine = render_state->composite_op.is_affine;
if (is_affine) {
if (!i830_get_transformed_coordinates(srcX, srcY,
if (!intel_get_transformed_coordinates(srcX, srcY,
intel->transform[0],
&src_x[0], &src_y[0]))
return;
if (!i830_get_transformed_coordinates(srcX, srcY + h,
if (!intel_get_transformed_coordinates(srcX, srcY + h,
intel->transform[0],
&src_x[1], &src_y[1]))
return;
if (!i830_get_transformed_coordinates(srcX + w, srcY + h,
if (!intel_get_transformed_coordinates(srcX + w, srcY + h,
intel->transform[0],
&src_x[2], &src_y[2]))
return;
} else {
if (!i830_get_transformed_coordinates_3d(srcX, srcY,
if (!intel_get_transformed_coordinates_3d(srcX, srcY,
intel->transform[0],
&src_x[0], &src_y[0],
&src_w[0]))
return;
if (!i830_get_transformed_coordinates_3d(srcX, srcY + h,
if (!intel_get_transformed_coordinates_3d(srcX, srcY + h,
intel->transform[0],
&src_x[1], &src_y[1],
&src_w[1]))
return;
if (!i830_get_transformed_coordinates_3d(srcX + w, srcY + h,
if (!intel_get_transformed_coordinates_3d(srcX + w, srcY + h,
intel->transform[0],
&src_x[2], &src_y[2],
&src_w[2]))
......@@ -1770,35 +1770,35 @@ i965_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY,
} else {
has_mask = TRUE;
if (is_affine) {
if (!i830_get_transformed_coordinates(maskX, maskY,
if (!intel_get_transformed_coordinates(maskX, maskY,
intel->
transform[1],
&mask_x[0],
&mask_y[0]))
return;
if (!i830_get_transformed_coordinates(maskX, maskY + h,
if (!intel_get_transformed_coordinates(maskX, maskY + h,
intel->
transform[1],
&mask_x[1],
&mask_y[1]))
return;
if (!i830_get_transformed_coordinates
if (!intel_get_transformed_coordinates
(maskX + w, maskY + h, intel->transform[1],
&mask_x[2], &mask_y[2]))
return;
} else {
if (!i830_get_transformed_coordinates_3d(maskX, maskY,
if (!intel_get_transformed_coordinates_3d(maskX, maskY,
intel->
transform[1],
&mask_x[0],
&mask_y[0],
&mask_w[0]))
return;
if (!i830_get_transformed_coordinates_3d
if (!intel_get_transformed_coordinates_3d
(maskX, maskY + h, intel->transform[1], &mask_x[1],
&mask_y[1], &mask_w[1]))
return;
if (!i830_get_transformed_coordinates_3d
if (!intel_get_transformed_coordinates_3d
(maskX + w, maskY + h, intel->transform[1],
&mask_x[2], &mask_y[2], &mask_w[2]))
return;
......
......@@ -35,10 +35,10 @@
#include "xf86xv.h"
#include "fourcc.h"
#include "i830.h"
#include "intel.h"
#include "intel_hwmc.h"
#include "intel_video.h"
#include "i830_reg.h"
#include "i830_video.h"
#include "i830_hwmc.h"
#include "i965_reg.h"
#include "brw_defines.h"
#include "brw_structs.h"
......@@ -365,7 +365,7 @@ static drm_intel_bo *i965_create_dst_surface_state(ScrnInfoPtr scrn,
{
intel_screen_private *intel = intel_get_screen_private(scrn);
struct brw_surface_state *dest_surf_state;
drm_intel_bo *pixmap_bo = i830_get_pixmap_bo(pixmap);
drm_intel_bo *pixmap_bo = intel_get_pixmap_bo(pixmap);
drm_intel_bo *surf_bo;
if (intel_alloc_and_map(intel, "textured video surface state", 4096,
......@@ -400,8 +400,8 @@ static drm_intel_bo *i965_create_dst_surface_state(ScrnInfoPtr scrn,
dest_surf_state->ss2.width = scrn->virtualX - 1;
dest_surf_state->ss2.mip_count = 0;
dest_surf_state->ss2.render_target_rotation = 0;
dest_surf_state->ss3.pitch = intel_get_pixmap_pitch(pixmap) - 1;
dest_surf_state->ss3.tiled_surface = i830_pixmap_tiled(pixmap);
dest_surf_state->ss3.pitch = intel_pixmap_pitch(pixmap) - 1;
dest_surf_state->ss3.tiled_surface = intel_pixmap_tiled(pixmap);
dest_surf_state->ss3.tile_walk = 0; /* TileX */
drm_intel_bo_unmap(surf_bo);
......@@ -1240,11 +1240,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn,
/* release reference once we're finished */
drm_intel_bo_unreference(bind_bo);
#if WATCH_STATS
/* i830_dump_error_state(scrn); */
#endif
i830_debug_flush(scrn);
intel_debug_flush(scrn);
}
void i965_free_video(ScrnInfoPtr scrn)
......
......@@ -72,12 +72,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "intel_driver.h"
#include "uxa.h"
Bool i830_uxa_init(ScreenPtr pScreen);
void i830_uxa_create_screen_resources(ScreenPtr pScreen);
void i830_uxa_block_handler(ScreenPtr pScreen);
Bool i830_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table,
int num_bos);
/* XXX
* The X server gained an *almost* identical implementation in 1.9.
*
......@@ -181,7 +175,7 @@ extern DevPrivateKeyRec uxa_pixmap_index;
extern int uxa_pixmap_index;
#endif
static inline struct intel_pixmap *i830_get_pixmap_intel(PixmapPtr pixmap)
static inline struct intel_pixmap *intel_get_pixmap_private(PixmapPtr pixmap)
{
#if HAS_DEVPRIVATEKEYREC
return dixGetPrivate(&pixmap->devPrivates, &uxa_pixmap_index);
......@@ -197,23 +191,23 @@ static inline Bool intel_pixmap_is_busy(struct intel_pixmap *priv)
return priv->busy;
}
static inline void i830_set_pixmap_intel(PixmapPtr pixmap, struct intel_pixmap *intel)
static inline void intel_set_pixmap_private(PixmapPtr pixmap, struct intel_pixmap *intel)
{
dixSetPrivate(&pixmap->devPrivates, &uxa_pixmap_index, intel);
}
static inline Bool i830_uxa_pixmap_is_dirty(PixmapPtr pixmap)
static inline Bool intel_pixmap_is_dirty(PixmapPtr pixmap)
{