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Chris Wilson authored
On older chipsets (i.e. pre-i965) tiling is very restrictive and imposes severe size and alignment constraints. Combine that with relatively small apertures and it is very easy to create a batch buffer that cannot be mapped into the aperture (but would otherwise fit based purely on total object size). To prevent this we need to not use tiling for large buffers (the very same buffers where tiling would be of most benefit!). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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