...
 
Commits (25)
......@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ([2.60])
AC_INIT([xf86-video-amdgpu],
[1.1.0],
[1.1.2],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-amdgpu])
......@@ -89,9 +89,9 @@ PKG_CHECK_EXISTS([xorg-server >= 1.16],
[sysconfigdir=""])
AC_ARG_WITH(xorg-conf-dir,
AS_HELP_STRING([--with-xorg-conf-dir=DIR],
[Default xorg.conf.d directory [[default=from $PKG_CONFIG xorg-server]]]),
[Default xorg.conf.d directory [[default=${prefix}/share/X11/xorg.conf.d]]]),
[configdir="$withval"],
[configdir="$sysconfigdir"])
[configdir='${prefix}/share/X11/xorg.conf.d'])
AC_SUBST(configdir)
AM_CONDITIONAL(HAS_XORG_CONF_DIR, [test "x$sysconfigdir" != "x"])
......@@ -279,6 +279,7 @@ echo " prefix: $prefix"
echo " exec_prefix: $exec_prefix"
echo " libdir: $libdir"
echo " includedir: $includedir"
echo " configdir: $configdir"
echo ""
echo " CFLAGS: $CFLAGS"
......
......@@ -29,7 +29,7 @@ RandR support up to version 1.4;
.SH SUPPORTED HARDWARE
The
.B amdgpu
driver supports CI and newer families' video cards.
driver supports SI and newer families' video cards.
.PD
.SH CONFIGURATION DETAILS
Please refer to __xconfigfile__(__filemansuffix__) for general configuration
......
......@@ -131,6 +131,35 @@ Bool amdgpu_bo_get_handle(struct amdgpu_buffer *bo, uint32_t *handle)
handle) == 0;
}
static void amdgpu_pixmap_do_get_tiling_info(PixmapPtr pixmap)
{
struct amdgpu_pixmap *priv = amdgpu_get_pixmap_private(pixmap);
ScreenPtr screen = pixmap->drawable.pScreen;
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn);
struct drm_amdgpu_gem_metadata gem_metadata;
gem_metadata.handle = priv->handle;
gem_metadata.op = AMDGPU_GEM_METADATA_OP_GET_METADATA;
if (drmCommandWriteRead(pAMDGPUEnt->fd, DRM_AMDGPU_GEM_METADATA,
&gem_metadata, sizeof(gem_metadata)) == 0)
priv->tiling_info = gem_metadata.data.tiling_info;
}
uint64_t amdgpu_pixmap_get_tiling_info(PixmapPtr pixmap)
{
struct amdgpu_pixmap *priv = amdgpu_get_pixmap_private(pixmap);
uint32_t handle;
if (!priv || !priv->handle_valid) {
amdgpu_pixmap_get_handle(pixmap, &handle);
priv = amdgpu_get_pixmap_private(pixmap);
}
return priv->tiling_info;
}
Bool amdgpu_pixmap_get_handle(PixmapPtr pixmap, uint32_t *handle)
{
#ifdef USE_GLAMOR
......@@ -162,13 +191,15 @@ Bool amdgpu_pixmap_get_handle(PixmapPtr pixmap, uint32_t *handle)
r = drmPrimeFDToHandle(pAMDGPUEnt->fd, fd, &priv->handle);
close(fd);
if (r == 0)
goto success;
goto get_tiling_info;
}
#endif
if (!priv->bo || !amdgpu_bo_get_handle(priv->bo, &priv->handle))
return FALSE;
get_tiling_info:
amdgpu_pixmap_do_get_tiling_info(pixmap);
success:
priv->handle_valid = TRUE;
*handle = priv->handle;
......@@ -345,21 +376,6 @@ struct amdgpu_buffer *amdgpu_gem_bo_open_prime(amdgpu_device_handle pDev,
#ifdef AMDGPU_PIXMAP_SHARING
Bool amdgpu_share_pixmap_backing(struct amdgpu_buffer *bo, void **handle_p)
{
int handle;
if (bo->flags & AMDGPU_BO_FLAGS_GBM)
handle = gbm_bo_get_fd(bo->bo.gbm);
else
amdgpu_bo_export(bo->bo.amdgpu,
amdgpu_bo_handle_type_dma_buf_fd,
(uint32_t *)&handle);
*handle_p = (void *)(long)handle;
return TRUE;
}
Bool amdgpu_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle)
{
ScrnInfoPtr pScrn = xf86ScreenToScrn(ppix->drawable.pScreen);
......
......@@ -31,14 +31,14 @@ extern struct amdgpu_buffer *amdgpu_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width
extern Bool amdgpu_bo_get_handle(struct amdgpu_buffer *bo, uint32_t *handle);
extern uint64_t amdgpu_pixmap_get_tiling_info(PixmapPtr pixmap);
extern Bool amdgpu_pixmap_get_handle(PixmapPtr pixmap, uint32_t *handle);
extern int amdgpu_bo_map(ScrnInfoPtr pScrn, struct amdgpu_buffer *bo);
extern void amdgpu_bo_unmap(struct amdgpu_buffer *bo);
extern Bool amdgpu_share_pixmap_backing(struct amdgpu_buffer *bo, void **handle_p);
extern Bool
amdgpu_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle);
......@@ -104,4 +104,20 @@ struct amdgpu_buffer *amdgpu_gem_bo_open_prime(amdgpu_device_handle pDev,
int fd_handle,
uint32_t size);
/**
* get_drawable_pixmap() returns the backing pixmap for a given drawable.
*
* @param drawable the drawable being requested.
*
* This function returns the backing pixmap for a drawable, whether it is a
* redirected window, unredirected window, or already a pixmap.
*/
static inline PixmapPtr get_drawable_pixmap(DrawablePtr drawable)
{
if (drawable->type == DRAWABLE_PIXMAP)
return (PixmapPtr)drawable;
else
return drawable->pScreen->GetWindowPixmap((WindowPtr)drawable);
}
#endif /* AMDGPU_BO_HELPER_H */
/* This file is autogenerated please do not edit */
static AMDGPUCardInfo AMDGPUCards[] = {
{ 0x6600, CHIP_FAMILY_OLAND },
{ 0x6601, CHIP_FAMILY_OLAND },
{ 0x6602, CHIP_FAMILY_OLAND },
{ 0x6603, CHIP_FAMILY_OLAND },
{ 0x6604, CHIP_FAMILY_OLAND },
{ 0x6605, CHIP_FAMILY_OLAND },
{ 0x6606, CHIP_FAMILY_OLAND },
{ 0x6607, CHIP_FAMILY_OLAND },
{ 0x6608, CHIP_FAMILY_OLAND },
{ 0x6610, CHIP_FAMILY_OLAND },
{ 0x6611, CHIP_FAMILY_OLAND },
{ 0x6613, CHIP_FAMILY_OLAND },
{ 0x6617, CHIP_FAMILY_OLAND },
{ 0x6620, CHIP_FAMILY_OLAND },
{ 0x6621, CHIP_FAMILY_OLAND },
{ 0x6623, CHIP_FAMILY_OLAND },
{ 0x6631, CHIP_FAMILY_OLAND },
{ 0x6660, CHIP_FAMILY_HAINAN },
{ 0x6663, CHIP_FAMILY_HAINAN },
{ 0x6664, CHIP_FAMILY_HAINAN },
{ 0x6665, CHIP_FAMILY_HAINAN },
{ 0x6667, CHIP_FAMILY_HAINAN },
{ 0x666F, CHIP_FAMILY_HAINAN },
{ 0x6780, CHIP_FAMILY_TAHITI },
{ 0x6784, CHIP_FAMILY_TAHITI },
{ 0x6788, CHIP_FAMILY_TAHITI },
{ 0x678A, CHIP_FAMILY_TAHITI },
{ 0x6790, CHIP_FAMILY_TAHITI },
{ 0x6791, CHIP_FAMILY_TAHITI },
{ 0x6792, CHIP_FAMILY_TAHITI },
{ 0x6798, CHIP_FAMILY_TAHITI },
{ 0x6799, CHIP_FAMILY_TAHITI },
{ 0x679A, CHIP_FAMILY_TAHITI },
{ 0x679B, CHIP_FAMILY_TAHITI },
{ 0x679E, CHIP_FAMILY_TAHITI },
{ 0x679F, CHIP_FAMILY_TAHITI },
{ 0x6800, CHIP_FAMILY_PITCAIRN },
{ 0x6801, CHIP_FAMILY_PITCAIRN },
{ 0x6802, CHIP_FAMILY_PITCAIRN },
{ 0x6806, CHIP_FAMILY_PITCAIRN },
{ 0x6808, CHIP_FAMILY_PITCAIRN },
{ 0x6809, CHIP_FAMILY_PITCAIRN },
{ 0x6810, CHIP_FAMILY_PITCAIRN },
{ 0x6811, CHIP_FAMILY_PITCAIRN },
{ 0x6816, CHIP_FAMILY_PITCAIRN },
{ 0x6817, CHIP_FAMILY_PITCAIRN },
{ 0x6818, CHIP_FAMILY_PITCAIRN },
{ 0x6819, CHIP_FAMILY_PITCAIRN },
{ 0x6820, CHIP_FAMILY_VERDE },
{ 0x6821, CHIP_FAMILY_VERDE },
{ 0x6822, CHIP_FAMILY_VERDE },
{ 0x6823, CHIP_FAMILY_VERDE },
{ 0x6824, CHIP_FAMILY_VERDE },
{ 0x6825, CHIP_FAMILY_VERDE },
{ 0x6826, CHIP_FAMILY_VERDE },
{ 0x6827, CHIP_FAMILY_VERDE },
{ 0x6828, CHIP_FAMILY_VERDE },
{ 0x6829, CHIP_FAMILY_VERDE },
{ 0x682A, CHIP_FAMILY_VERDE },
{ 0x682B, CHIP_FAMILY_VERDE },
{ 0x682C, CHIP_FAMILY_VERDE },
{ 0x682D, CHIP_FAMILY_VERDE },
{ 0x682F, CHIP_FAMILY_VERDE },
{ 0x6830, CHIP_FAMILY_VERDE },
{ 0x6831, CHIP_FAMILY_VERDE },
{ 0x6835, CHIP_FAMILY_VERDE },
{ 0x6837, CHIP_FAMILY_VERDE },
{ 0x6838, CHIP_FAMILY_VERDE },
{ 0x6839, CHIP_FAMILY_VERDE },
{ 0x683B, CHIP_FAMILY_VERDE },
{ 0x683D, CHIP_FAMILY_VERDE },
{ 0x683F, CHIP_FAMILY_VERDE },
{ 0x684C, CHIP_FAMILY_PITCAIRN },
{ 0x6640, CHIP_FAMILY_BONAIRE },
{ 0x6641, CHIP_FAMILY_BONAIRE },
{ 0x6646, CHIP_FAMILY_BONAIRE },
{ 0x6647, CHIP_FAMILY_BONAIRE },
{ 0x6649, CHIP_FAMILY_BONAIRE },
{ 0x6650, CHIP_FAMILY_BONAIRE },
{ 0x6651, CHIP_FAMILY_BONAIRE },
......@@ -25,6 +100,22 @@ static AMDGPUCardInfo AMDGPUCards[] = {
{ 0x983D, CHIP_FAMILY_KABINI },
{ 0x983E, CHIP_FAMILY_KABINI },
{ 0x983F, CHIP_FAMILY_KABINI },
{ 0x9850, CHIP_FAMILY_MULLINS },
{ 0x9851, CHIP_FAMILY_MULLINS },
{ 0x9852, CHIP_FAMILY_MULLINS },
{ 0x9853, CHIP_FAMILY_MULLINS },
{ 0x9854, CHIP_FAMILY_MULLINS },
{ 0x9855, CHIP_FAMILY_MULLINS },
{ 0x9856, CHIP_FAMILY_MULLINS },
{ 0x9857, CHIP_FAMILY_MULLINS },
{ 0x9858, CHIP_FAMILY_MULLINS },
{ 0x9859, CHIP_FAMILY_MULLINS },
{ 0x985A, CHIP_FAMILY_MULLINS },
{ 0x985B, CHIP_FAMILY_MULLINS },
{ 0x985C, CHIP_FAMILY_MULLINS },
{ 0x985D, CHIP_FAMILY_MULLINS },
{ 0x985E, CHIP_FAMILY_MULLINS },
{ 0x985F, CHIP_FAMILY_MULLINS },
{ 0x1304, CHIP_FAMILY_KAVERI },
{ 0x1305, CHIP_FAMILY_KAVERI },
{ 0x1306, CHIP_FAMILY_KAVERI },
......@@ -43,6 +134,7 @@ static AMDGPUCardInfo AMDGPUCards[] = {
{ 0x1315, CHIP_FAMILY_KAVERI },
{ 0x1316, CHIP_FAMILY_KAVERI },
{ 0x1317, CHIP_FAMILY_KAVERI },
{ 0x1318, CHIP_FAMILY_KAVERI },
{ 0x131B, CHIP_FAMILY_KAVERI },
{ 0x131C, CHIP_FAMILY_KAVERI },
{ 0x131D, CHIP_FAMILY_KAVERI },
......@@ -80,11 +172,23 @@ static AMDGPUCardInfo AMDGPUCards[] = {
{ 0x7300, CHIP_FAMILY_FIJI },
{ 0x98E4, CHIP_FAMILY_STONEY },
{ 0x67E0, CHIP_FAMILY_POLARIS11 },
{ 0x67E1, CHIP_FAMILY_POLARIS11 },
{ 0x67E3, CHIP_FAMILY_POLARIS11 },
{ 0x67E8, CHIP_FAMILY_POLARIS11 },
{ 0x67E9, CHIP_FAMILY_POLARIS11 },
{ 0x67EB, CHIP_FAMILY_POLARIS11 },
{ 0x67EF, CHIP_FAMILY_POLARIS11 },
{ 0x67FF, CHIP_FAMILY_POLARIS11 },
{ 0x67E1, CHIP_FAMILY_POLARIS11 },
{ 0x67E7, CHIP_FAMILY_POLARIS11 },
{ 0x67E9, CHIP_FAMILY_POLARIS11 },
{ 0x67C0, CHIP_FAMILY_POLARIS10 },
{ 0x67C1, CHIP_FAMILY_POLARIS10 },
{ 0x67C2, CHIP_FAMILY_POLARIS10 },
{ 0x67C4, CHIP_FAMILY_POLARIS10 },
{ 0x67C7, CHIP_FAMILY_POLARIS10 },
{ 0x67DF, CHIP_FAMILY_POLARIS10 },
{ 0x67C8, CHIP_FAMILY_POLARIS10 },
{ 0x67C9, CHIP_FAMILY_POLARIS10 },
{ 0x67CA, CHIP_FAMILY_POLARIS10 },
{ 0x67CC, CHIP_FAMILY_POLARIS10 },
{ 0x67CF, CHIP_FAMILY_POLARIS10 },
};
/* This file is autogenerated please do not edit */
SymTabRec AMDGPUChipsets[] = {
{ PCI_CHIP_OLAND_6600, "OLAND" },
{ PCI_CHIP_OLAND_6601, "OLAND" },
{ PCI_CHIP_OLAND_6602, "OLAND" },
{ PCI_CHIP_OLAND_6603, "OLAND" },
{ PCI_CHIP_OLAND_6604, "OLAND" },
{ PCI_CHIP_OLAND_6605, "OLAND" },
{ PCI_CHIP_OLAND_6606, "OLAND" },
{ PCI_CHIP_OLAND_6607, "OLAND" },
{ PCI_CHIP_OLAND_6608, "OLAND" },
{ PCI_CHIP_OLAND_6610, "OLAND" },
{ PCI_CHIP_OLAND_6611, "OLAND" },
{ PCI_CHIP_OLAND_6613, "OLAND" },
{ PCI_CHIP_OLAND_6617, "OLAND" },
{ PCI_CHIP_OLAND_6620, "OLAND" },
{ PCI_CHIP_OLAND_6621, "OLAND" },
{ PCI_CHIP_OLAND_6623, "OLAND" },
{ PCI_CHIP_OLAND_6631, "OLAND" },
{ PCI_CHIP_HAINAN_6660, "HAINAN" },
{ PCI_CHIP_HAINAN_6663, "HAINAN" },
{ PCI_CHIP_HAINAN_6664, "HAINAN" },
{ PCI_CHIP_HAINAN_6665, "HAINAN" },
{ PCI_CHIP_HAINAN_6667, "HAINAN" },
{ PCI_CHIP_HAINAN_666F, "HAINAN" },
{ PCI_CHIP_TAHITI_6780, "TAHITI" },
{ PCI_CHIP_TAHITI_6784, "TAHITI" },
{ PCI_CHIP_TAHITI_6788, "TAHITI" },
{ PCI_CHIP_TAHITI_678A, "TAHITI" },
{ PCI_CHIP_TAHITI_6790, "TAHITI" },
{ PCI_CHIP_TAHITI_6791, "TAHITI" },
{ PCI_CHIP_TAHITI_6792, "TAHITI" },
{ PCI_CHIP_TAHITI_6798, "TAHITI" },
{ PCI_CHIP_TAHITI_6799, "TAHITI" },
{ PCI_CHIP_TAHITI_679A, "TAHITI" },
{ PCI_CHIP_TAHITI_679B, "TAHITI" },
{ PCI_CHIP_TAHITI_679E, "TAHITI" },
{ PCI_CHIP_TAHITI_679F, "TAHITI" },
{ PCI_CHIP_PITCAIRN_6800, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6801, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6802, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6806, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6808, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6809, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6810, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6811, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6816, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6817, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6818, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6819, "PITCAIRN" },
{ PCI_CHIP_VERDE_6820, "VERDE" },
{ PCI_CHIP_VERDE_6821, "VERDE" },
{ PCI_CHIP_VERDE_6822, "VERDE" },
{ PCI_CHIP_VERDE_6823, "VERDE" },
{ PCI_CHIP_VERDE_6824, "VERDE" },
{ PCI_CHIP_VERDE_6825, "VERDE" },
{ PCI_CHIP_VERDE_6826, "VERDE" },
{ PCI_CHIP_VERDE_6827, "VERDE" },
{ PCI_CHIP_VERDE_6828, "VERDE" },
{ PCI_CHIP_VERDE_6829, "VERDE" },
{ PCI_CHIP_VERDE_682A, "VERDE" },
{ PCI_CHIP_VERDE_682B, "VERDE" },
{ PCI_CHIP_VERDE_682C, "VERDE" },
{ PCI_CHIP_VERDE_682D, "VERDE" },
{ PCI_CHIP_VERDE_682F, "VERDE" },
{ PCI_CHIP_VERDE_6830, "VERDE" },
{ PCI_CHIP_VERDE_6831, "VERDE" },
{ PCI_CHIP_VERDE_6835, "VERDE" },
{ PCI_CHIP_VERDE_6837, "VERDE" },
{ PCI_CHIP_VERDE_6838, "VERDE" },
{ PCI_CHIP_VERDE_6839, "VERDE" },
{ PCI_CHIP_VERDE_683B, "VERDE" },
{ PCI_CHIP_VERDE_683D, "VERDE" },
{ PCI_CHIP_VERDE_683F, "VERDE" },
{ PCI_CHIP_PITCAIRN_684C, "PITCAIRN" },
{ PCI_CHIP_BONAIRE_6640, "BONAIRE" },
{ PCI_CHIP_BONAIRE_6641, "BONAIRE" },
{ PCI_CHIP_BONAIRE_6646, "BONAIRE" },
{ PCI_CHIP_BONAIRE_6647, "BONAIRE" },
{ PCI_CHIP_BONAIRE_6649, "BONAIRE" },
{ PCI_CHIP_BONAIRE_6650, "BONAIRE" },
{ PCI_CHIP_BONAIRE_6651, "BONAIRE" },
......@@ -25,6 +100,22 @@ SymTabRec AMDGPUChipsets[] = {
{ PCI_CHIP_KABINI_983D, "KABINI" },
{ PCI_CHIP_KABINI_983E, "KABINI" },
{ PCI_CHIP_KABINI_983F, "KABINI" },
{ PCI_CHIP_MULLINS_9850, "MULLINS" },
{ PCI_CHIP_MULLINS_9851, "MULLINS" },
{ PCI_CHIP_MULLINS_9852, "MULLINS" },
{ PCI_CHIP_MULLINS_9853, "MULLINS" },
{ PCI_CHIP_MULLINS_9854, "MULLINS" },
{ PCI_CHIP_MULLINS_9855, "MULLINS" },
{ PCI_CHIP_MULLINS_9856, "MULLINS" },
{ PCI_CHIP_MULLINS_9857, "MULLINS" },
{ PCI_CHIP_MULLINS_9858, "MULLINS" },
{ PCI_CHIP_MULLINS_9859, "MULLINS" },
{ PCI_CHIP_MULLINS_985A, "MULLINS" },
{ PCI_CHIP_MULLINS_985B, "MULLINS" },
{ PCI_CHIP_MULLINS_985C, "MULLINS" },
{ PCI_CHIP_MULLINS_985D, "MULLINS" },
{ PCI_CHIP_MULLINS_985E, "MULLINS" },
{ PCI_CHIP_MULLINS_985F, "MULLINS" },
{ PCI_CHIP_KAVERI_1304, "KAVERI" },
{ PCI_CHIP_KAVERI_1305, "KAVERI" },
{ PCI_CHIP_KAVERI_1306, "KAVERI" },
......@@ -43,6 +134,7 @@ SymTabRec AMDGPUChipsets[] = {
{ PCI_CHIP_KAVERI_1315, "KAVERI" },
{ PCI_CHIP_KAVERI_1316, "KAVERI" },
{ PCI_CHIP_KAVERI_1317, "KAVERI" },
{ PCI_CHIP_KAVERI_1318, "KAVERI" },
{ PCI_CHIP_KAVERI_131B, "KAVERI" },
{ PCI_CHIP_KAVERI_131C, "KAVERI" },
{ PCI_CHIP_KAVERI_131D, "KAVERI" },
......@@ -80,12 +172,24 @@ SymTabRec AMDGPUChipsets[] = {
{ PCI_CHIP_FIJI_7300, "FIJI" },
{ PCI_CHIP_STONEY_98E4, "STONEY" },
{ PCI_CHIP_POLARIS11_67E0, "POLARIS11" },
{ PCI_CHIP_POLARIS11_67E1, "POLARIS11" },
{ PCI_CHIP_POLARIS11_67E3, "POLARIS11" },
{ PCI_CHIP_POLARIS11_67E8, "POLARIS11" },
{ PCI_CHIP_POLARIS11_67E9, "POLARIS11" },
{ PCI_CHIP_POLARIS11_67EB, "POLARIS11" },
{ PCI_CHIP_POLARIS11_67EF, "POLARIS11" },
{ PCI_CHIP_POLARIS11_67FF, "POLARIS11" },
{ PCI_CHIP_POLARIS11_67E1, "POLARIS11" },
{ PCI_CHIP_POLARIS11_67E7, "POLARIS11" },
{ PCI_CHIP_POLARIS11_67E9, "POLARIS11" },
{ PCI_CHIP_POLARIS10_67C0, "POLARIS10" },
{ PCI_CHIP_POLARIS10_67C1, "POLARIS10" },
{ PCI_CHIP_POLARIS10_67C2, "POLARIS10" },
{ PCI_CHIP_POLARIS10_67C4, "POLARIS10" },
{ PCI_CHIP_POLARIS10_67C7, "POLARIS10" },
{ PCI_CHIP_POLARIS10_67DF, "POLARIS10" },
{ PCI_CHIP_POLARIS10_67C8, "POLARIS10" },
{ PCI_CHIP_POLARIS10_67C9, "POLARIS10" },
{ PCI_CHIP_POLARIS10_67CA, "POLARIS10" },
{ PCI_CHIP_POLARIS10_67CC, "POLARIS10" },
{ PCI_CHIP_POLARIS10_67CF, "POLARIS10" },
{ -1, NULL }
};
......@@ -98,63 +98,6 @@ amdgpu_get_flink_name(AMDGPUEntPtr pAMDGPUEnt, PixmapPtr pixmap, uint32_t *name)
return TRUE;
}
static PixmapPtr get_drawable_pixmap(DrawablePtr drawable)
{
if (drawable->type == DRAWABLE_PIXMAP)
return (PixmapPtr) drawable;
else
return (*drawable->pScreen->
GetWindowPixmap) ((WindowPtr) drawable);
}
static PixmapPtr fixup_glamor(DrawablePtr drawable, PixmapPtr pixmap)
{
PixmapPtr old = get_drawable_pixmap(drawable);
ScreenPtr screen = drawable->pScreen;
struct amdgpu_pixmap *priv = amdgpu_get_pixmap_private(pixmap);
GCPtr gc;
/* With a glamor pixmap, 2D pixmaps are created in texture
* and without a static BO attached to it. To support DRI,
* we need to create a new textured-drm pixmap and
* need to copy the original content to this new textured-drm
* pixmap, and then convert the old pixmap to a coherent
* textured-drm pixmap which has a valid BO attached to it
* and also has a valid texture, thus both glamor and DRI2
* can access it.
*
*/
/* Copy the current contents of the pixmap to the bo. */
gc = GetScratchGC(drawable->depth, screen);
if (gc) {
ValidateGC(&pixmap->drawable, gc);
gc->ops->CopyArea(&old->drawable, &pixmap->drawable,
gc,
0, 0,
old->drawable.width,
old->drawable.height, 0, 0);
FreeScratchGC(gc);
}
amdgpu_set_pixmap_private(pixmap, NULL);
/* And redirect the pixmap to the new bo (for 3D). */
glamor_egl_exchange_buffers(old, pixmap);
amdgpu_set_pixmap_private(old, priv);
old->refcnt++;
screen->ModifyPixmapHeader(old,
old->drawable.width,
old->drawable.height,
0, 0, pixmap->devKind, NULL);
old->devPrivate.ptr = NULL;
screen->DestroyPixmap(pixmap);
return old;
}
static BufferPtr
amdgpu_dri2_create_buffer2(ScreenPtr pScreen,
DrawablePtr drawable,
......@@ -226,8 +169,10 @@ amdgpu_dri2_create_buffer2(ScreenPtr pScreen,
goto error;
if (pixmap) {
if (is_glamor_pixmap)
pixmap = fixup_glamor(drawable, pixmap);
if (is_glamor_pixmap) {
pixmap = amdgpu_glamor_set_pixmap_bo(drawable, pixmap);
pixmap->refcnt++;
}
if (!amdgpu_get_flink_name(pAMDGPUEnt, pixmap, &buffers->name))
goto error;
......@@ -457,10 +402,11 @@ static uint32_t amdgpu_get_msc_delta(DrawablePtr pDraw, xf86CrtcPtr crtc)
*/
static Bool amdgpu_dri2_get_crtc_msc(xf86CrtcPtr crtc, CARD64 *ust, CARD64 *msc)
{
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
if (!amdgpu_crtc_is_enabled(crtc) ||
drmmode_crtc_get_ust_msc(crtc, ust, msc) != Success) {
/* CRTC is not running, extrapolate MSC and timestamp */
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
ScrnInfoPtr scrn = crtc->scrn;
AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn);
CARD64 now, delta_t, delta_seq;
......@@ -485,6 +431,8 @@ static Bool amdgpu_dri2_get_crtc_msc(xf86CrtcPtr crtc, CARD64 *ust, CARD64 *msc)
*msc += delta_seq;
}
*msc += drmmode_crtc->interpolated_vblanks;
return TRUE;
}
......@@ -709,7 +657,7 @@ amdgpu_dri2_exchange_buffers(DrawablePtr draw, DRI2BufferPtr front,
region.extents.x1 = region.extents.y1 = 0;
region.extents.x2 = front_priv->pixmap->drawable.width;
region.extents.y2 = front_priv->pixmap->drawable.width;
region.extents.y2 = front_priv->pixmap->drawable.height;
region.data = NULL;
DamageRegionAppend(&front_priv->pixmap->drawable, &region);
......@@ -935,7 +883,8 @@ static int amdgpu_dri2_get_msc(DrawablePtr draw, CARD64 * ust, CARD64 * msc)
if (!amdgpu_dri2_get_crtc_msc(crtc, ust, msc))
return FALSE;
*msc += amdgpu_get_msc_delta(draw, crtc);
if (draw && draw->type == DRAWABLE_WINDOW)
*msc += get_dri2_window_priv((WindowPtr)draw)->vblank_delta;
*msc &= 0xffffffff;
return TRUE;
}
......
......@@ -272,18 +272,92 @@ fallback_pixmap:
return fbCreatePixmap(screen, w, h, depth, usage);
}
PixmapPtr
amdgpu_glamor_set_pixmap_bo(DrawablePtr drawable, PixmapPtr pixmap)
{
PixmapPtr old = get_drawable_pixmap(drawable);
ScreenPtr screen = drawable->pScreen;
struct amdgpu_pixmap *priv = amdgpu_get_pixmap_private(pixmap);
GCPtr gc;
/* With a glamor pixmap, 2D pixmaps are created in texture
* and without a static BO attached to it. To support DRI,
* we need to create a new textured-drm pixmap and
* need to copy the original content to this new textured-drm
* pixmap, and then convert the old pixmap to a coherent
* textured-drm pixmap which has a valid BO attached to it
* and also has a valid texture, thus both glamor and DRI2
* can access it.
*
*/
/* Copy the current contents of the pixmap to the bo. */
gc = GetScratchGC(drawable->depth, screen);
if (gc) {
ValidateGC(&pixmap->drawable, gc);
gc->ops->CopyArea(&old->drawable, &pixmap->drawable,
gc,
0, 0,
old->drawable.width,
old->drawable.height, 0, 0);
FreeScratchGC(gc);
}
amdgpu_set_pixmap_private(pixmap, NULL);
/* And redirect the pixmap to the new bo (for 3D). */
glamor_egl_exchange_buffers(old, pixmap);
amdgpu_set_pixmap_private(old, priv);
screen->ModifyPixmapHeader(old,
old->drawable.width,
old->drawable.height,
0, 0, pixmap->devKind, NULL);
old->devPrivate.ptr = NULL;
screen->DestroyPixmap(pixmap);
return old;
}
#ifdef AMDGPU_PIXMAP_SHARING
static Bool
amdgpu_glamor_share_pixmap_backing(PixmapPtr pixmap, ScreenPtr slave,
void **handle_p)
{
struct amdgpu_pixmap *priv = amdgpu_get_pixmap_private(pixmap);
ScreenPtr screen = pixmap->drawable.pScreen;
uint64_t tiling_info;
CARD16 stride;
CARD32 size;
int fd;
tiling_info = amdgpu_pixmap_get_tiling_info(pixmap);
if (AMDGPU_TILING_GET(tiling_info, ARRAY_MODE) != 0) {
PixmapPtr linear;
/* We don't want to re-allocate the screen pixmap as
* linear, to avoid trouble with page flipping
*/
if (screen->GetScreenPixmap(screen) == pixmap)
return FALSE;
if (!priv)
linear = screen->CreatePixmap(screen, pixmap->drawable.width,
pixmap->drawable.height,
pixmap->drawable.depth,
CREATE_PIXMAP_USAGE_SHARED);
if (!linear)
return FALSE;
amdgpu_glamor_set_pixmap_bo(&pixmap->drawable, linear);
}
fd = glamor_fd_from_pixmap(screen, pixmap, &stride, &size);
if (fd < 0)
return FALSE;
return amdgpu_share_pixmap_backing(priv->bo, handle_p);
*handle_p = (void *)(long)fd;
return TRUE;
}
static Bool
......
......@@ -71,6 +71,7 @@ void amdgpu_glamor_finish(ScrnInfoPtr pScrn);
Bool
amdgpu_glamor_create_textured_pixmap(PixmapPtr pixmap, struct amdgpu_pixmap *priv);
void amdgpu_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst);
PixmapPtr amdgpu_glamor_set_pixmap_bo(DrawablePtr drawable, PixmapPtr pixmap);
XF86VideoAdaptorPtr amdgpu_glamor_xv_init(ScreenPtr pScreen, int num_adapt);
......
......@@ -39,24 +39,6 @@
#include "amdgpu_pixmap.h"
/**
* get_drawable_pixmap() returns the backing pixmap for a given drawable.
*
* @param pDrawable the drawable being requested.
*
* This function returns the backing pixmap for a drawable, whether it is a
* redirected window, unredirected window, or already a pixmap.
*/
static PixmapPtr
get_drawable_pixmap(DrawablePtr pDrawable)
{
if (pDrawable->type == DRAWABLE_WINDOW)
return pDrawable->pScreen->
GetWindowPixmap((WindowPtr) pDrawable);
else
return (PixmapPtr) pDrawable;
}
/* Are there any outstanding GPU operations for this pixmap? */
static Bool
amdgpu_glamor_gpu_pending(uint_fast32_t gpu_synced, uint_fast32_t gpu_access)
......
......@@ -167,7 +167,6 @@ static Bool AMDGPUCreateScreenResources_KMS(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
AMDGPUInfoPtr info = AMDGPUPTR(pScrn);
rrScrPrivPtr rrScrPriv = rrGetScrPriv(pScreen);
PixmapPtr pixmap;
pScreen->CreateScreenResources = info->CreateScreenResources;
......@@ -176,17 +175,21 @@ static Bool AMDGPUCreateScreenResources_KMS(ScreenPtr pScreen)
pScreen->CreateScreenResources = AMDGPUCreateScreenResources_KMS;
/* Set the RandR primary output if Xorg hasn't */
if (
if (dixPrivateKeyRegistered(rrPrivKey)) {
rrScrPrivPtr rrScrPriv = rrGetScrPriv(pScreen);
if (
#ifdef AMDGPU_PIXMAP_SHARING
!pScreen->isGPU &&
!pScreen->isGPU &&
#endif
!rrScrPriv->primaryOutput)
{
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
!rrScrPriv->primaryOutput)
{
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
rrScrPriv->primaryOutput = xf86_config->output[0]->randr_output;
RROutputChanged(rrScrPriv->primaryOutput, FALSE);
rrScrPriv->layoutChanged = TRUE;
rrScrPriv->primaryOutput = xf86_config->output[0]->randr_output;
RROutputChanged(rrScrPriv->primaryOutput, FALSE);
rrScrPriv->layoutChanged = TRUE;
}
}
if (!drmmode_set_desired_modes(pScrn, &info->drmmode, pScrn->is_gpu))
......@@ -758,8 +761,11 @@ static void AMDGPUSetupCapabilities(ScrnInfoPtr pScrn)
if (ret == 0) {
if (value & DRM_PRIME_CAP_EXPORT)
pScrn->capabilities |= RR_Capability_SourceOutput | RR_Capability_SinkOffload;
if (value & DRM_PRIME_CAP_IMPORT)
pScrn->capabilities |= RR_Capability_SinkOutput | RR_Capability_SourceOffload;
if (value & DRM_PRIME_CAP_IMPORT) {
pScrn->capabilities |= RR_Capability_SourceOffload;
if (info->drmmode.count_crtcs)
pScrn->capabilities |= RR_Capability_SinkOutput;
}
}
#endif
}
......@@ -873,8 +879,6 @@ Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int flags)
amdgpu_drm_queue_init();
AMDGPUSetupCapabilities(pScrn);
/* don't enable tiling if accel is not enabled */
if (info->use_glamor) {
/* set default group bytes, overridden by kernel info below */
......@@ -928,13 +932,21 @@ Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int flags)
goto fail;
}
AMDGPUSetupCapabilities(pScrn);
if (info->drmmode.count_crtcs == 1)
pAMDGPUEnt->HasCRTC2 = FALSE;
else
pAMDGPUEnt->HasCRTC2 = TRUE;
info->cursor_w = CURSOR_WIDTH_CIK;
info->cursor_h = CURSOR_HEIGHT_CIK;
if (info->ChipFamily >= CHIP_FAMILY_TAHITI &&
info->ChipFamily <= CHIP_FAMILY_HAINAN) {
info->cursor_w = CURSOR_WIDTH;
info->cursor_h = CURSOR_HEIGHT;
} else {
info->cursor_w = CURSOR_WIDTH_CIK;
info->cursor_h = CURSOR_HEIGHT_CIK;
}
amdgpu_query_heap_size(pAMDGPUEnt->pDev, AMDGPU_GEM_DOMAIN_GTT,
&heap_size, &max_allocation);
......
/* This file is autogenerated please do not edit */
static PciChipsets AMDGPUPciChipsets[] = {
{ PCI_CHIP_OLAND_6600, PCI_CHIP_OLAND_6600, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6601, PCI_CHIP_OLAND_6601, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6602, PCI_CHIP_OLAND_6602, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6603, PCI_CHIP_OLAND_6603, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6604, PCI_CHIP_OLAND_6604, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6605, PCI_CHIP_OLAND_6605, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6606, PCI_CHIP_OLAND_6606, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6607, PCI_CHIP_OLAND_6607, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6608, PCI_CHIP_OLAND_6608, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6610, PCI_CHIP_OLAND_6610, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6611, PCI_CHIP_OLAND_6611, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6613, PCI_CHIP_OLAND_6613, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6617, PCI_CHIP_OLAND_6617, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6620, PCI_CHIP_OLAND_6620, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6621, PCI_CHIP_OLAND_6621, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6623, PCI_CHIP_OLAND_6623, RES_SHARED_VGA },
{ PCI_CHIP_OLAND_6631, PCI_CHIP_OLAND_6631, RES_SHARED_VGA },
{ PCI_CHIP_HAINAN_6660, PCI_CHIP_HAINAN_6660, RES_SHARED_VGA },
{ PCI_CHIP_HAINAN_6663, PCI_CHIP_HAINAN_6663, RES_SHARED_VGA },
{ PCI_CHIP_HAINAN_6664, PCI_CHIP_HAINAN_6664, RES_SHARED_VGA },
{ PCI_CHIP_HAINAN_6665, PCI_CHIP_HAINAN_6665, RES_SHARED_VGA },
{ PCI_CHIP_HAINAN_6667, PCI_CHIP_HAINAN_6667, RES_SHARED_VGA },
{ PCI_CHIP_HAINAN_666F, PCI_CHIP_HAINAN_666F, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6780, PCI_CHIP_TAHITI_6780, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6784, PCI_CHIP_TAHITI_6784, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6788, PCI_CHIP_TAHITI_6788, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_678A, PCI_CHIP_TAHITI_678A, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6790, PCI_CHIP_TAHITI_6790, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6791, PCI_CHIP_TAHITI_6791, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6792, PCI_CHIP_TAHITI_6792, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6798, PCI_CHIP_TAHITI_6798, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6799, PCI_CHIP_TAHITI_6799, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_679A, PCI_CHIP_TAHITI_679A, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_679B, PCI_CHIP_TAHITI_679B, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_679E, PCI_CHIP_TAHITI_679E, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_679F, PCI_CHIP_TAHITI_679F, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6800, PCI_CHIP_PITCAIRN_6800, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6801, PCI_CHIP_PITCAIRN_6801, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6802, PCI_CHIP_PITCAIRN_6802, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6806, PCI_CHIP_PITCAIRN_6806, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6808, PCI_CHIP_PITCAIRN_6808, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6809, PCI_CHIP_PITCAIRN_6809, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6810, PCI_CHIP_PITCAIRN_6810, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6811, PCI_CHIP_PITCAIRN_6811, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6816, PCI_CHIP_PITCAIRN_6816, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6817, PCI_CHIP_PITCAIRN_6817, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6818, PCI_CHIP_PITCAIRN_6818, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6819, PCI_CHIP_PITCAIRN_6819, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6820, PCI_CHIP_VERDE_6820, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6821, PCI_CHIP_VERDE_6821, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6822, PCI_CHIP_VERDE_6822, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6823, PCI_CHIP_VERDE_6823, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6824, PCI_CHIP_VERDE_6824, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6825, PCI_CHIP_VERDE_6825, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6826, PCI_CHIP_VERDE_6826, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6827, PCI_CHIP_VERDE_6827, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6828, PCI_CHIP_VERDE_6828, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6829, PCI_CHIP_VERDE_6829, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_682A, PCI_CHIP_VERDE_682A, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_682B, PCI_CHIP_VERDE_682B, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_682C, PCI_CHIP_VERDE_682C, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_682D, PCI_CHIP_VERDE_682D, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_682F, PCI_CHIP_VERDE_682F, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6830, PCI_CHIP_VERDE_6830, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6831, PCI_CHIP_VERDE_6831, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6835, PCI_CHIP_VERDE_6835, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6837, PCI_CHIP_VERDE_6837, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6838, PCI_CHIP_VERDE_6838, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6839, PCI_CHIP_VERDE_6839, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_683B, PCI_CHIP_VERDE_683B, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_683D, PCI_CHIP_VERDE_683D, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_683F, PCI_CHIP_VERDE_683F, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_684C, PCI_CHIP_PITCAIRN_684C, RES_SHARED_VGA },
{ PCI_CHIP_BONAIRE_6640, PCI_CHIP_BONAIRE_6640, RES_SHARED_VGA },
{ PCI_CHIP_BONAIRE_6641, PCI_CHIP_BONAIRE_6641, RES_SHARED_VGA },
{ PCI_CHIP_BONAIRE_6646, PCI_CHIP_BONAIRE_6646, RES_SHARED_VGA },
{ PCI_CHIP_BONAIRE_6647, PCI_CHIP_BONAIRE_6647, RES_SHARED_VGA },
{ PCI_CHIP_BONAIRE_6649, PCI_CHIP_BONAIRE_6649, RES_SHARED_VGA },
{ PCI_CHIP_BONAIRE_6650, PCI_CHIP_BONAIRE_6650, RES_SHARED_VGA },
{ PCI_CHIP_BONAIRE_6651, PCI_CHIP_BONAIRE_6651, RES_SHARED_VGA },
......@@ -25,6 +100,22 @@ static PciChipsets AMDGPUPciChipsets[] = {
{ PCI_CHIP_KABINI_983D, PCI_CHIP_KABINI_983D, RES_SHARED_VGA },
{ PCI_CHIP_KABINI_983E, PCI_CHIP_KABINI_983E, RES_SHARED_VGA },
{ PCI_CHIP_KABINI_983F, PCI_CHIP_KABINI_983F, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_9850, PCI_CHIP_MULLINS_9850, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_9851, PCI_CHIP_MULLINS_9851, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_9852, PCI_CHIP_MULLINS_9852, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_9853, PCI_CHIP_MULLINS_9853, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_9854, PCI_CHIP_MULLINS_9854, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_9855, PCI_CHIP_MULLINS_9855, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_9856, PCI_CHIP_MULLINS_9856, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_9857, PCI_CHIP_MULLINS_9857, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_9858, PCI_CHIP_MULLINS_9858, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_9859, PCI_CHIP_MULLINS_9859, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_985A, PCI_CHIP_MULLINS_985A, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_985B, PCI_CHIP_MULLINS_985B, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_985C, PCI_CHIP_MULLINS_985C, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_985D, PCI_CHIP_MULLINS_985D, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_985E, PCI_CHIP_MULLINS_985E, RES_SHARED_VGA },
{ PCI_CHIP_MULLINS_985F, PCI_CHIP_MULLINS_985F, RES_SHARED_VGA },
{ PCI_CHIP_KAVERI_1304, PCI_CHIP_KAVERI_1304, RES_SHARED_VGA },
{ PCI_CHIP_KAVERI_1305, PCI_CHIP_KAVERI_1305, RES_SHARED_VGA },
{ PCI_CHIP_KAVERI_1306, PCI_CHIP_KAVERI_1306, RES_SHARED_VGA },
......@@ -43,6 +134,7 @@ static PciChipsets AMDGPUPciChipsets[] = {
{ PCI_CHIP_KAVERI_1315, PCI_CHIP_KAVERI_1315, RES_SHARED_VGA },
{ PCI_CHIP_KAVERI_1316, PCI_CHIP_KAVERI_1316, RES_SHARED_VGA },
{ PCI_CHIP_KAVERI_1317, PCI_CHIP_KAVERI_1317, RES_SHARED_VGA },
{ PCI_CHIP_KAVERI_1318, PCI_CHIP_KAVERI_1318, RES_SHARED_VGA },
{ PCI_CHIP_KAVERI_131B, PCI_CHIP_KAVERI_131B, RES_SHARED_VGA },
{ PCI_CHIP_KAVERI_131C, PCI_CHIP_KAVERI_131C, RES_SHARED_VGA },
{ PCI_CHIP_KAVERI_131D, PCI_CHIP_KAVERI_131D, RES_SHARED_VGA },
......@@ -80,12 +172,24 @@ static PciChipsets AMDGPUPciChipsets[] = {
{ PCI_CHIP_FIJI_7300, PCI_CHIP_FIJI_7300, RES_SHARED_VGA },
{ PCI_CHIP_STONEY_98E4, PCI_CHIP_STONEY_98E4, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS11_67E0, PCI_CHIP_POLARIS11_67E0, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS11_67E1, PCI_CHIP_POLARIS11_67E1, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS11_67E3, PCI_CHIP_POLARIS11_67E3, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS11_67E8, PCI_CHIP_POLARIS11_67E8, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS11_67E9, PCI_CHIP_POLARIS11_67E9, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS11_67EB, PCI_CHIP_POLARIS11_67EB, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS11_67EF, PCI_CHIP_POLARIS11_67EF, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS11_67FF, PCI_CHIP_POLARIS11_67FF, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS11_67E1, PCI_CHIP_POLARIS11_67E1, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS11_67E7, PCI_CHIP_POLARIS11_67E7, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS11_67E9, PCI_CHIP_POLARIS11_67E9, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS10_67C0, PCI_CHIP_POLARIS10_67C0, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS10_67C1, PCI_CHIP_POLARIS10_67C1, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS10_67C2, PCI_CHIP_POLARIS10_67C2, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS10_67C4, PCI_CHIP_POLARIS10_67C4, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS10_67C7, PCI_CHIP_POLARIS10_67C7, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS10_67DF, PCI_CHIP_POLARIS10_67DF, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS10_67C8, PCI_CHIP_POLARIS10_67C8, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS10_67C9, PCI_CHIP_POLARIS10_67C9, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS10_67CA, PCI_CHIP_POLARIS10_67CA, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS10_67CC, PCI_CHIP_POLARIS10_67CC, RES_SHARED_VGA },
{ PCI_CHIP_POLARIS10_67CF, PCI_CHIP_POLARIS10_67CF, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
/* This file is autogenerated please do not edit */
static const struct pci_id_match amdgpu_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6600, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6601, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6602, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6603, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6604, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6605, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6606, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6607, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6608, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6610, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6611, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6613, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6617, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6620, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6621, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6623, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6631, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6660, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6663, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6664, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6665, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6667, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_666F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6780, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6784, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6788, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_678A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6790, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6791, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6792, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6798, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6799, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679E, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6800, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6801, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6802, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6806, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6808, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6809, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6810, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6811, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6816, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6817, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6818, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6819, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6820, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6821, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6822, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6823, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6824, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6825, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6826, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6827, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6828, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6829, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682C, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682D, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6830, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6831, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6835, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6837, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6838, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6839, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683D, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_684C, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6640, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6641, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6646, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6647, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6649, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6650, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6651, 0 ),
......@@ -25,6 +100,22 @@ static const struct pci_id_match amdgpu_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983D, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983E, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9850, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9851, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9852, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9853, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9854, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9855, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9856, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9857, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9858, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9859, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985C, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985D, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985E, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1304, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1305, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1306, 0 ),
......@@ -43,6 +134,7 @@ static const struct pci_id_match amdgpu_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1315, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1316, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1317, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1318, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131C, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131D, 0 ),
......@@ -80,12 +172,24 @@ static const struct pci_id_match amdgpu_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_FIJI_7300, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_STONEY_98E4, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E0, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E1, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E3, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E8, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E9, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67EB, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67EF, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67FF, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E1, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E7, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E9, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C0, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C1, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C2, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C4, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C7, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67DF, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C8, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C9, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67CA, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67CC, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67CF, 0 ),
{ 0, 0, 0 }
};
......@@ -32,6 +32,8 @@ struct amdgpu_pixmap {
uint_fast32_t gpu_read;
uint_fast32_t gpu_write;
uint64_t tiling_info;
struct amdgpu_buffer *bo;
/* GEM handle for pixmaps shared via DRI2/3 */
......
......@@ -58,10 +58,16 @@ typedef enum {
CHIP_FAMILY_UNKNOW,
CHIP_FAMILY_LEGACY,
CHIP_FAMILY_AMDGPU,
CHIP_FAMILY_TAHITI,
CHIP_FAMILY_PITCAIRN,
CHIP_FAMILY_VERDE,
CHIP_FAMILY_OLAND,
CHIP_FAMILY_HAINAN,
CHIP_FAMILY_BONAIRE,
CHIP_FAMILY_KAVERI,
CHIP_FAMILY_KABINI,
CHIP_FAMILY_HAWAII,
CHIP_FAMILY_MULLINS,
CHIP_FAMILY_TOPAZ,
CHIP_FAMILY_TONGA,
CHIP_FAMILY_CARRIZO,
......
#define PCI_CHIP_OLAND_6600 0x6600
#define PCI_CHIP_OLAND_6601 0x6601
#define PCI_CHIP_OLAND_6602 0x6602
#define PCI_CHIP_OLAND_6603 0x6603
#define PCI_CHIP_OLAND_6604 0x6604
#define PCI_CHIP_OLAND_6605 0x6605
#define PCI_CHIP_OLAND_6606 0x6606
#define PCI_CHIP_OLAND_6607 0x6607
#define PCI_CHIP_OLAND_6608 0x6608
#define PCI_CHIP_OLAND_6610 0x6610
#define PCI_CHIP_OLAND_6611 0x6611
#define PCI_CHIP_OLAND_6613 0x6613
#define PCI_CHIP_OLAND_6617 0x6617
#define PCI_CHIP_OLAND_6620 0x6620
#define PCI_CHIP_OLAND_6621 0x6621
#define PCI_CHIP_OLAND_6623 0x6623
#define PCI_CHIP_OLAND_6631 0x6631
#define PCI_CHIP_HAINAN_6660 0x6660
#define PCI_CHIP_HAINAN_6663 0x6663
#define PCI_CHIP_HAINAN_6664 0x6664
#define PCI_CHIP_HAINAN_6665 0x6665
#define PCI_CHIP_HAINAN_6667 0x6667
#define PCI_CHIP_HAINAN_666F 0x666F
#define PCI_CHIP_TAHITI_6780 0x6780
#define PCI_CHIP_TAHITI_6784 0x6784
#define PCI_CHIP_TAHITI_6788 0x6788
#define PCI_CHIP_TAHITI_678A 0x678A
#define PCI_CHIP_TAHITI_6790 0x6790
#define PCI_CHIP_TAHITI_6791 0x6791
#define PCI_CHIP_TAHITI_6792 0x6792
#define PCI_CHIP_TAHITI_6798 0x6798
#define PCI_CHIP_TAHITI_6799 0x6799
#define PCI_CHIP_TAHITI_679A 0x679A
#define PCI_CHIP_TAHITI_679B 0x679B
#define PCI_CHIP_TAHITI_679E 0x679E
#define PCI_CHIP_TAHITI_679F 0x679F
#define PCI_CHIP_PITCAIRN_6800 0x6800
#define PCI_CHIP_PITCAIRN_6801 0x6801
#define PCI_CHIP_PITCAIRN_6802 0x6802
#define PCI_CHIP_PITCAIRN_6806 0x6806
#define PCI_CHIP_PITCAIRN_6808 0x6808
#define PCI_CHIP_PITCAIRN_6809 0x6809
#define PCI_CHIP_PITCAIRN_6810 0x6810
#define PCI_CHIP_PITCAIRN_6811 0x6811
#define PCI_CHIP_PITCAIRN_6816 0x6816
#define PCI_CHIP_PITCAIRN_6817 0x6817
#define PCI_CHIP_PITCAIRN_6818 0x6818
#define PCI_CHIP_PITCAIRN_6819 0x6819
#define PCI_CHIP_VERDE_6820 0x6820
#define PCI_CHIP_VERDE_6821 0x6821
#define PCI_CHIP_VERDE_6822 0x6822
#define PCI_CHIP_VERDE_6823 0x6823
#define PCI_CHIP_VERDE_6824 0x6824
#define PCI_CHIP_VERDE_6825 0x6825
#define PCI_CHIP_VERDE_6826 0x6826
#define PCI_CHIP_VERDE_6827 0x6827
#define PCI_CHIP_VERDE_6828 0x6828
#define PCI_CHIP_VERDE_6829 0x6829
#define PCI_CHIP_VERDE_682A 0x682A
#define PCI_CHIP_VERDE_682B 0x682B
#define PCI_CHIP_VERDE_682C 0x682C
#define PCI_CHIP_VERDE_682D 0x682D
#define PCI_CHIP_VERDE_682F 0x682F
#define PCI_CHIP_VERDE_6830 0x6830
#define PCI_CHIP_VERDE_6831 0x6831
#define PCI_CHIP_VERDE_6835 0x6835
#define PCI_CHIP_VERDE_6837 0x6837
#define PCI_CHIP_VERDE_6838 0x6838
#define PCI_CHIP_VERDE_6839 0x6839
#define PCI_CHIP_VERDE_683B 0x683B
#define PCI_CHIP_VERDE_683D 0x683D
#define PCI_CHIP_VERDE_683F 0x683F
#define PCI_CHIP_PITCAIRN_684C 0x684C
#define PCI_CHIP_BONAIRE_6640 0x6640
#define PCI_CHIP_BONAIRE_6641 0x6641
#define PCI_CHIP_BONAIRE_6646 0x6646
#define PCI_CHIP_BONAIRE_6647 0x6647
#define PCI_CHIP_BONAIRE_6649 0x6649
#define PCI_CHIP_BONAIRE_6650 0x6650
#define PCI_CHIP_BONAIRE_6651 0x6651
......@@ -23,6 +98,22 @@
#define PCI_CHIP_KABINI_983D 0x983D
#define PCI_CHIP_KABINI_983E 0x983E
#define PCI_CHIP_KABINI_983F 0x983F
#define PCI_CHIP_MULLINS_9850 0x9850
#define PCI_CHIP_MULLINS_9851 0x9851
#define PCI_CHIP_MULLINS_9852 0x9852
#define PCI_CHIP_MULLINS_9853 0x9853
#define PCI_CHIP_MULLINS_9854 0x9854
#define PCI_CHIP_MULLINS_9855 0x9855
#define PCI_CHIP_MULLINS_9856 0x9856
#define PCI_CHIP_MULLINS_9857 0x9857
#define PCI_CHIP_MULLINS_9858 0x9858
#define PCI_CHIP_MULLINS_9859 0x9859
#define PCI_CHIP_MULLINS_985A 0x985A
#define PCI_CHIP_MULLINS_985B 0x985B
#define PCI_CHIP_MULLINS_985C 0x985C
#define PCI_CHIP_MULLINS_985D 0x985D
#define PCI_CHIP_MULLINS_985E 0x985E
#define PCI_CHIP_MULLINS_985F 0x985F
#define PCI_CHIP_KAVERI_1304 0x1304
#define PCI_CHIP_KAVERI_1305 0x1305
#define PCI_CHIP_KAVERI_1306 0x1306
......@@ -41,6 +132,7 @@
#define PCI_CHIP_KAVERI_1315 0x1315
#define PCI_CHIP_KAVERI_1316 0x1316
#define PCI_CHIP_KAVERI_1317 0x1317
#define PCI_CHIP_KAVERI_1318 0x1318
#define PCI_CHIP_KAVERI_131B 0x131B
#define PCI_CHIP_KAVERI_131C 0x131C
#define PCI_CHIP_KAVERI_131D 0x131D
......@@ -78,10 +170,22 @@
#define PCI_CHIP_FIJI_7300 0x7300
#define PCI_CHIP_STONEY_98E4 0x98E4
#define PCI_CHIP_POLARIS11_67E0 0x67E0
#define PCI_CHIP_POLARIS11_67E1 0x67E1
#define PCI_CHIP_POLARIS11_67E3 0x67E3
#define PCI_CHIP_POLARIS11_67E8 0x67E8
#define PCI_CHIP_POLARIS11_67E9 0x67E9
#define PCI_CHIP_POLARIS11_67EB 0x67EB
#define PCI_CHIP_POLARIS11_67EF 0x67EF
#define PCI_CHIP_POLARIS11_67FF 0x67FF
#define PCI_CHIP_POLARIS11_67E1 0x67E1
#define PCI_CHIP_POLARIS11_67E7 0x67E7
#define PCI_CHIP_POLARIS11_67E9 0x67E9
#define PCI_CHIP_POLARIS10_67C0 0x67C0
#define PCI_CHIP_POLARIS10_67C1 0x67C1
#define PCI_CHIP_POLARIS10_67C2 0x67C2
#define PCI_CHIP_POLARIS10_67C4 0x67C4
#define PCI_CHIP_POLARIS10_67C7 0x67C7
#define PCI_CHIP_POLARIS10_67DF 0x67DF
#define PCI_CHIP_POLARIS10_67C8 0x67C8
#define PCI_CHIP_POLARIS10_67C9 0x67C9
#define PCI_CHIP_POLARIS10_67CA 0x67CA
#define PCI_CHIP_POLARIS10_67CC 0x67CC
#define PCI_CHIP_POLARIS10_67CF 0x67CF
......@@ -36,6 +36,7 @@
#include "damagestr.h"
#include "micmap.h"
#include "xf86cmap.h"
#include "xf86Priv.h"
#include "sarea.h"
#include "drmmode_display.h"
......@@ -2159,8 +2160,10 @@ void drmmode_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
void drmmode_fini(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
{
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(pScrn);
AMDGPUInfoPtr info = AMDGPUPTR(pScrn);
int c;
if (!info->drmmode_inited)
return;
......@@ -2171,6 +2174,14 @@ void drmmode_fini(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
RemoveBlockAndWakeupHandlers((BlockHandlerProcPtr) NoopDDA,
drm_wakeup_handler, drmmode);
}
for (c = 0; c < config->num_crtc; c++) {
xf86CrtcPtr crtc = config->crtc[c];
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
drmmode_crtc_scanout_destroy(&info->drmmode, &drmmode_crtc->scanout[0]);
drmmode_crtc_scanout_destroy(&info->drmmode, &drmmode_crtc->scanout[1]);
}
}
void drmmode_set_cursor(ScrnInfoPtr scrn, drmmode_ptr drmmode, int id,
......@@ -2362,9 +2373,10 @@ amdgpu_mode_hotplug(ScrnInfoPtr scrn, drmmode_ptr drmmode)
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn);
AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn);
drmModeResPtr mode_res;
int i, j;
int i, j, s;
Bool found;
Bool changed = FALSE;
int num_dvi = 0, num_hdmi = 0;
mode_res = drmModeGetResources(pAMDGPUEnt->fd);
if (!mode_res)
......@@ -2400,24 +2412,47 @@ restart_destroy:
for (i = 0; i < mode_res->count_connectors; i++) {
found = FALSE;
for (j = 0; j < config->num_output; j++) {
xf86OutputPtr output = config->output[j];
drmmode_output_private_ptr drmmode_output;
for (s = 0; !found && s < xf86NumScreens; s++) {
ScrnInfoPtr loop_scrn = xf86Screens[s];
xf86CrtcConfigPtr loop_config =
XF86_CRTC_CONFIG_PTR(loop_scrn);
drmmode_output = output->driver_private;
if (mode_res->connectors[i] == drmmode_output->output_id) {
found = TRUE;
break;
if (strcmp(loop_scrn->driverName, scrn->driverName) ||
AMDGPUEntPriv(loop_scrn) != pAMDGPUEnt)
continue;
for (j = 0; !found && j < loop_config->num_output; j++) {
xf86OutputPtr output = loop_config->output[j];
drmmode_output_private_ptr drmmode_output;
drmmode_output = output->driver_private;
if (mode_res->connectors[i] ==
drmmode_output->output_id) {
found = TRUE;
switch(drmmode_output->mode_output->connector_type) {
case DRM_MODE_CONNECTOR_DVII:
case DRM_MODE_CONNECTOR_DVID:
case DRM_MODE_CONNECTOR_DVIA:
num_dvi++;
break;
case DRM_MODE_CONNECTOR_HDMIA:
case DRM_MODE_CONNECTOR_HDMIB:
num_hdmi++;
break;
}
}
}
}
if (found)
continue;
changed = TRUE;
drmmode_output_init(scrn, drmmode, mode_res, i, NULL, NULL, 1);
if (drmmode_output_init(scrn, drmmode, mode_res, i, &num_dvi,
&num_hdmi, 1) != 0)
changed = TRUE;
}
if (changed) {
if (changed && dixPrivateKeyRegistered(rrPrivKey)) {
#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,14,99,2,0)
RRSetChanged(xf86ScrnToScreen(scrn));
#else
......
"#pciid","define","family","name"
"0x6600","OLAND_6600","OLAND","OLAND"
"0x6601","OLAND_6601","OLAND","OLAND"
"0x6602","OLAND_6602","OLAND","OLAND"
"0x6603","OLAND_6603","OLAND","OLAND"
"0x6604","OLAND_6604","OLAND","OLAND"
"0x6605","OLAND_6605","OLAND","OLAND"
"0x6606","OLAND_6606","OLAND","OLAND"
"0x6607","OLAND_6607","OLAND","OLAND"
"0x6608","OLAND_6608","OLAND","OLAND"
"0x6610","OLAND_6610","OLAND","OLAND"
"0x6611","OLAND_6611","OLAND","OLAND"
"0x6613","OLAND_6613","OLAND","OLAND"
"0x6617","OLAND_6617","OLAND","OLAND"
"0x6620","OLAND_6620","OLAND","OLAND"
"0x6621","OLAND_6621","OLAND","OLAND"
"0x6623","OLAND_6623","OLAND","OLAND"
"0x6631","OLAND_6631","OLAND","OLAND"
"0x6660","HAINAN_6660","HAINAN","HAINAN"
"0x6663","HAINAN_6663","HAINAN","HAINAN"
"0x6664","HAINAN_6664","HAINAN","HAINAN"
"0x6665","HAINAN_6665","HAINAN","HAINAN"
"0x6667","HAINAN_6667","HAINAN","HAINAN"
"0x666F","HAINAN_666F","HAINAN","HAINAN"
"0x6780","TAHITI_6780","TAHITI","TAHITI"
"0x6784","TAHITI_6784","TAHITI","TAHITI"
"0x6788","TAHITI_6788","TAHITI","TAHITI"
"0x678A","TAHITI_678A","TAHITI","TAHITI"
"0x6790","TAHITI_6790","TAHITI","TAHITI"
"0x6791","TAHITI_6791","TAHITI","TAHITI"
"0x6792","TAHITI_6792","TAHITI","TAHITI"
"0x6798","TAHITI_6798","TAHITI","TAHITI"
"0x6799","TAHITI_6799","TAHITI","TAHITI"
"0x679A","TAHITI_679A","TAHITI","TAHITI"
"0x679B","TAHITI_679B","TAHITI","TAHITI"
"0x679E","TAHITI_679E","TAHITI","TAHITI"
"0x679F","TAHITI_679F","TAHITI","TAHITI"
"0x6800","PITCAIRN_6800","PITCAIRN","PITCAIRN"
"0x6801","PITCAIRN_6801","PITCAIRN","PITCAIRN"
"0x6802","PITCAIRN_6802","PITCAIRN","PITCAIRN"
"0x6806","PITCAIRN_6806","PITCAIRN","PITCAIRN"
"0x6808","PITCAIRN_6808","PITCAIRN","PITCAIRN"
"0x6809","PITCAIRN_6809","PITCAIRN","PITCAIRN"
"0x6810","PITCAIRN_6810","PITCAIRN","PITCAIRN"
"0x6811","PITCAIRN_6811","PITCAIRN","PITCAIRN"
"0x6816","PITCAIRN_6816","PITCAIRN","PITCAIRN"
"0x6817","PITCAIRN_6817","PITCAIRN","PITCAIRN"
"0x6818","PITCAIRN_6818","PITCAIRN","PITCAIRN"
"0x6819","PITCAIRN_6819","PITCAIRN","PITCAIRN"
"0x6820","VERDE_6820","VERDE","VERDE"
"0x6821","VERDE_6821","VERDE","VERDE"
"0x6822","VERDE_6822","VERDE","VERDE"
"0x6823","VERDE_6823","VERDE","VERDE"
"0x6824","VERDE_6824","VERDE","VERDE"
"0x6825","VERDE_6825","VERDE","VERDE"
"0x6826","VERDE_6826","VERDE","VERDE"
"0x6827","VERDE_6827","VERDE","VERDE"
"0x6828","VERDE_6828","VERDE","VERDE"
"0x6829","VERDE_6829","VERDE","VERDE"
"0x682A","VERDE_682A","VERDE","VERDE"
"0x682B","VERDE_682B","VERDE","VERDE"
"0x682C","VERDE_682C","VERDE","VERDE"
"0x682D","VERDE_682D","VERDE","VERDE"
"0x682F","VERDE_682F","VERDE","VERDE"
"0x6830","VERDE_6830","VERDE","VERDE"
"0x6831","VERDE_6831","VERDE","VERDE"
"0x6835","VERDE_6835","VERDE","VERDE"
"0x6837","VERDE_6837","VERDE","VERDE"
"0x6838","VERDE_6838","VERDE","VERDE"
"0x6839","VERDE_6839","VERDE","VERDE"
"0x683B","VERDE_683B","VERDE","VERDE"
"0x683D","VERDE_683D","VERDE","VERDE"
"0x683F","VERDE_683F","VERDE","VERDE"
"0x684C","PITCAIRN_684C","PITCAIRN","PITCAIRN"
"0x6640","BONAIRE_6640","BONAIRE","BONAIRE"
"0x6641","BONAIRE_6641","BONAIRE","BONAIRE"
"0x6646","BONAIRE_6646","BONAIRE","BONAIRE"
"0x6647","BONAIRE_6647","BONAIRE","BONAIRE"
"0x6649","BONAIRE_6649","BONAIRE","BONAIRE"
"0x6650","BONAIRE_6650","BONAIRE","BONAIRE"
"0x6651","BONAIRE_6651","BONAIRE","BONAIRE"
......@@ -24,6 +99,22 @@
"0x983D","KABINI_983D","KABINI","KABINI"
"0x983E","KABINI_983E","KABINI","KABINI"
"0x983F","KABINI_983F","KABINI","KABINI"
"0x9850","MULLINS_9850","MULLINS","MULLINS"
"0x9851","MULLINS_9851","MULLINS","MULLINS"
"0x9852","MULLINS_9852","MULLINS","MULLINS"
"0x9853","MULLINS_9853","MULLINS","MULLINS"
"0x9854","MULLINS_9854","MULLINS","MULLINS"
"0x9855","MULLINS_9855","MULLINS","MULLINS"
"0x9856","MULLINS_9856","MULLINS","MULLINS"
"0x9857","MULLINS_9857","MULLINS","MULLINS"
"0x9858","MULLINS_9858","MULLINS","MULLINS"
"0x9859","MULLINS_9859","MULLINS","MULLINS"
"0x985A","MULLINS_985A","MULLINS","MULLINS"
"0x985B","MULLINS_985B","MULLINS","MULLINS"
"0x985C","MULLINS_985C","MULLINS","MULLINS"
"0x985D","MULLINS_985D","MULLINS","MULLINS"
"0x985E","MULLINS_985E","MULLINS","MULLINS"
"0x985F","MULLINS_985F","MULLINS","MULLINS"
"0x1304","KAVERI_1304","KAVERI","KAVERI"
"0x1305","KAVERI_1305","KAVERI","KAVERI"
"0x1306","KAVERI_1306","KAVERI","KAVERI"
......@@ -42,6 +133,7 @@
"0x1315","KAVERI_1315","KAVERI","KAVERI"
"0x1316","KAVERI_1316","KAVERI","KAVERI"
"0x1317","KAVERI_1317","KAVERI","KAVERI"
"0x1318","KAVERI_1318","KAVERI","KAVERI"
"0x131B","KAVERI_131B","KAVERI","KAVERI"
"0x131C","KAVERI_131C","KAVERI","KAVERI"
"0x131D","KAVERI_131D","KAVERI","KAVERI"
......@@ -79,10 +171,22 @@
"0x7300","FIJI_7300","FIJI","FIJI"
"0x98E4","STONEY_98E4","STONEY","STONEY"
"0x67E0","POLARIS11_67E0","POLARIS11","POLARIS11"
"0x67E1","POLARIS11_67E1","POLARIS11","POLARIS11"
"0x67E3","POLARIS11_67E3","POLARIS11","POLARIS11"
"0x67E8","POLARIS11_67E8","POLARIS11","POLARIS11"
"0x67E9","POLARIS11_67E9","POLARIS11","POLARIS11"
"0x67EB","POLARIS11_67EB","POLARIS11","POLARIS11"
"0x67EF","POLARIS11_67EF","POLARIS11","POLARIS11"
"0x67FF","POLARIS11_67FF","POLARIS11","POLARIS11"
"0x67E1","POLARIS11_67E1","POLARIS11","POLARIS11"
"0x67E7","POLARIS11_67E7","POLARIS11","POLARIS11"
"0x67E9","POLARIS11_67E9","POLARIS11","POLARIS11"
"0x67C0","POLARIS10_67C0","POLARIS10","POLARIS10"
"0x67C1","POLARIS10_67C1","POLARIS10","POLARIS10"
"0x67C2","POLARIS10_67C2","POLARIS10","POLARIS10"
"0x67C4","POLARIS10_67C4","POLARIS10","POLARIS10"
"0x67C7","POLARIS10_67C7","POLARIS10","POLARIS10"
"0x67DF","POLARIS10_67DF","POLARIS10","POLARIS10"
"0x67C8","POLARIS10_67C8","POLARIS10","POLARIS10"
"0x67C9","POLARIS10_67C9","POLARIS10","POLARIS10"
"0x67CA","POLARIS10_67CA","POLARIS10","POLARIS10"
"0x67CC","POLARIS10_67CC","POLARIS10","POLARIS10"
"0x67CF","POLARIS10_67CF","POLARIS10","POLARIS10"